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PDF CDP1806AC Data sheet ( Hoja de datos )

Número de pieza CDP1806AC
Descripción CMOS 8-Bit Microprocessor
Fabricantes GE 
Logotipo GE Logotipo



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No Preview Available ! CDP1806AC Hoja de datos, Descripción, Manual

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1800-Series Microprocessors and Microcomputers
TERMINAL ASSIGNMENT
CLOCK
WAiT
'00
1<m
Ei:'Ei:R
..."0
,
"0
BUS 1
BUS 6
BUS ~
BUS 4
BUS 3
...,,BUS 2
BUS I
BUS 0
.0
'"
""""
"'"""""'"'"iiif'Eiiiiijji'
".."..""".."
."" ••0
"m
" rn
"22 mm
TOP VIEW
*ME ""0" CDPI805AC
Yoo FOR CDPIB06AC 92CS,35004
CDP1805AC, CDP1806AC
CMOS a-Bit Microprocessor With
On-Chip RAM" and Counter/Timer
Performance Features:
• Instruction time of 3.2 fJS,
-40 to +85°C
• 123 instructions - upwards software
compatible with CDP1802
• BCD arithmetic instructions
• Low-power IDLE mode
• Pin com{!atible with CDP1802
except for terminal 16
• 64K-byte memory address capability
• 64 bytes of on-chip RAM'"
• 16 x 16 matrix of on-board registers
• On-chip crystal or RC
controlled oscillator
• 8-bit Counter/Timer
",CDP1805AC only
The RCA-CDP1805AC and CDP1806AC are functional and
performance enhancements of the CDP1802 CMOS 8-bit
register-oriented microprocessor series and are designed
for use in general-purpose applications
The CDP180SAC hardware enhancements Include a 64-
byte RAM and an 8-bit presettable down counter. The
Counter/Timer which generates an internal interrupt
request, can be programmed for use in time-base, event-
counting, and pulse-duration measurement applications.
The Counter/Timer underflow output can also be directed
to the 0 output terminal. The CDP1806AC hardware
enhancements are identical to the CDP180SAC, except the
CDP1806AC contains no on-chip RAM.
The CDP180SAC and CDP1806AC are identical to the
CDP1804AC, except for the on-chip memory, and may be
used for CDP1804AC development purposes.
The CDP180SAC and CDP1806AC software enhancements
include 32 more instructions that the CDP1802. The 32 new
software instructions add subroutine call and return
capability, enhanced data transfer manipulation,
Counter/Timer control, improved interrupt handling,
single-instruction loop counting, and BCD arithmetic.
Upwards software and hardware compatibility is maintained
when substituting a CDP180fiAC or CDP1806AC for other
CDP1800-series microprocessors. Pinout is identical except
for the replacement of Vee with ME on the CDP180SAC and
the replacement of Vee with Voo on the CDP1806AC.
The CDP180SAC and CDP1806AC have an operating voltage
range of 4 V to 6.S V and are supplied in a 40-lead hermetic
dual-in-line ceramic package (0 suffix). 40-lead dual-in-
line plastic package (E suffix) and 44-lead plastic chip-
carrier (PCC) package (0 suffix).
ADDRESS BUS
- - - - --I
r-------, r - - - - - - - - --, :
~, 7
r-MA~MA4-'
COPleSI
PIO
MAD
CONTROL
CPD1S0SAC WITH
RAM,COUNTER/TIMER
COPI8D6AC WITH
COUNTER I TI MER
iiWR
CDPl833
I K BYTE ROM
I
I
---.I MAD
I
I 32coB~I~E2~AM
I (USED WITH 1
I ICDPIS06AC ONLY)
1-
--~MWR
II
OUT TPA I I
II
--~cs
I
L-su"soT- -BUrS4- ~
,I II
--1' - - - - - - - - - " ' " ' ' - - - - - - - - - - - --.J I
L _ _ _ _ _ _ _ _ _---.:8:...-c..:B:...'T.:...,::D::,ATc::Ac..:B:2:U:::-S_ _ _ _ _ _ _ _ _ _ _ _ _
92CM-34987RI
Fig. 1 - TYPical CDPI805AC, CDP1806AC small microprocessor system.
IfJ
File Number 1370
__________________________________________________________________ 85

1 page




CDP1806AC pdf
________________ 1800-Serles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
n " ""1 71 01
I
21 31 41 51
71
TPB
MEMORY
ADDRESS
I IHIGH BVTE
Miiii - - - ,
r+1
I ILOW BYTE
I
I
HIGH BYTE
I
I
I"L-
LOW BYTE
iiiii
I
I~
* ME IN
(HIGH)
I
I
~DATA BUS
DATA LATCHED IN CPU
I
i
~
VALID OATA FROM CPU
~
* FOR CDPI805AC ONLY
92CS-34990
Fig. 4 - External memory operation timing waveforms for CDP1805AC and CDP1806AC.
IfI
ENHANCED CDP1805AC and CDP1806AC OPERATION
TIMING
Timing for the CDP180SAC and CDP1806AC is the same as
the CDP1802 microprocessor series, with the following
exceptions:
o 4.S clock cycles are provided for memory access
instead of S.
o 0 changes 1/2 clock cycle earlier during the SEQ and
REO instructions.
• Flag lines (EF1-U4) are sampled at the end of the SO
cycle instead of at the beginning of the Sl cycle.
• Pause can only occur on the low-to-hgh transition of
either TPA or TPB, instead of any negative clock transition.
SPECIAL FEATURES
Schmitt triggers are provided on all inputs, except fiifE: and
BUS O-BUS 7, for maximum Immunity from noise and slow
signal transitions. A Schmitt trigger in the oscillator section
allows operation with an RC or crystal.
The CDP1802-series LOAD mode is not retained. This
mode (WATT, CLEAR=O) is not allowed on the CDP180SAC
and CDP1806AC.
A low power mode is provided, which is initiated via the
IDLE instruction. In this mode all external signals, except
the oscillator, are stopped on the low-to-high transition of
TPB. All outputs remain in their previous states, MRD is set
to a logic "1", and the data bus floats. The IDLE mode is
exited by a DMA or INT condition. The INT includes both
external interrupts and interrupts generated by the
Counter/Timer. The only restrictions are that the Timer
mode, which uses the TPA ..;- 32 clock source, and the
underflow condition of the Pulse Width Measurement
modes are not available to exit the IDLE mode.
SIGNAL DESCRIPTIONS
BUS 0 to BUS 7 (Data Bu.):
8-bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory, the microprocessor,
and 110 devices.
NO to N2 (110) Line.:
Activated by an 110 instruction to signal the 110 control
logic of a data transfer between memory and 110 interface.
These lines can be used to issue command codes or device
selection codes to the 110 devices. The N bits are low at all
times except when an 110 instruction is being executed.
During this time their state is the same as the corresponding
bits in the N register. The direction of data flow is defined in
the 110 instruction by bit N3 (internally) and is indicated by
the level of the 1iil1fD signal:
MRD = Voo: Input data from I/O to CPU and Memory
MRD = Vss: Output data from Memory to I/O
____________________~---------------------------------------------------------89

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CDP1806AC arduino
________________ 1800-8erle8 Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
PAUSE
Pause is a low power mode which stops the internal CPU
timing generator and freezes the state of the processor. The
CPU may be held in the Pause mode indefinitely. Hardware
pause can occur at two points in a machine cycle, on the
low-to-high transition of either TPA or TPB. A TPB pause
can also be initiated by software with the execution of an
IDLE instruction. In the pause mode. the oscillator continues
to run but subsequent clock transitions are ignored. TPA
and TPB remain at their previous state (see Fig. 11).
Pause is entered from RUN by dropping WAIT low.
Appropriate Setup and Hold times must be met.
If Pause is entered while in the event counter mode, the
appropriate Flag transition will continue to decrement the
counter.
Hardware-initiated pause is exited to RUN by raising the
Wait line high. Pause entered with an IDLE instruction
requires DMA, INTERRUPT or RESET to resumeexecution.
TPA PAUSE TIMING
RUN
May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation at the
point it left off. If paused at TPA, it will resume on the' next
high-to-Iow clock transition, while if paused at TPB, it will
resume on the next low-to-hlgh clock transition (see Fig.
11). When initiated from the Reset operation, the first
machine cycle following Reset is always the initialization
cycle. The initialization cycle is then followed by a DMA
(S2) cycle or fetch (SO) from location 0000 in memory.
SCHMITT TRIGGER INPUTS
All inputs except BUS O-BUS 7 and ME contain a Schmitt
Trigger circuit, which is especially useful on the CLEAR
input as a power-up RESET (see Fig. 10) and the CLOCK
input (see Figs. 7 and 8).
STATE TRANSITIONS
The CDP1805A and CDP1806A state transitions are shown
in Fig. 12. Each machine cycle requires the same period of
time, 8 clock pulses, except the initialization cycle (INIT)
which requires 9 clock pulses. Reset is asynchronous and
can be forced at any time.
TPA PAUSE TIMING
CLOCK
TPA
I F_'PHL
TPB PAUSE TIMING
TPB PAUSE TIMING
CLOCK
TPB
92CM- 31944"1
NOTE:
PAUSE (IN CLOCK WAVEFORM) WHILE REPRESENTED HERE AS ONE
CLOCK CYCLE IN DURATION, COULD BE INFINITELY LONG.
Fig. 11 - Pause mode timing waveforms.
PAIDIUTY RESET
FORCE so, 51
DiiA IN
~OUT
Fig. 12 - State transition diagram.
________________________________________________________________ 95

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