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Número de pieza ACPL-796J
Descripción Optically Isolated Sigma-Delta Modulator
Fabricantes AVAGO 
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ACPL-796J
Optically Isolated Sigma-Delta Modulator
Data Sheet
Description
The ACPL-796J is a 1-bit, second-order sigma-delta ()
modulator converts an analog input signal into a high-
speed data stream with galvanic isolation based on optical
coupling technology. The ACPL-796J operates from a 5 V
power supply with dynamic range of 80 dB with an appro-
priate digital filter. The differential inputs of ±200 mV (full
scale ±320 mV) are ideal for direct connection to shunt
resistors or other low-level signal sources in applications
such as motor phase current measurement.
The analog input is continuously sampled by means of
sigma-delta over-sampling using external clock, coupled
across the isolation barrier, which allows synchronous
operation with any digital controller. The signal infor-
mation is contained in the modulator data, as a density
of ones with data rate up to 20 MHz, and the data are
encoded and transmitted across the isolation boundary
where they are recovered and decoded into high-speed
data stream of digital ones and zeros. The original signal
information can be reconstructed with a digital filter. The
serial interface has a wide supply range of 3 V to 5.5 V.
Combined with superior optical coupling technology,
the modulator delivers high noise margins and excellent
immunity against isolation-mode transients. With 0.5 mm
minimum distance through insulation (DTI), the ACPL-796J
provides reliable double protection and high working
insulation voltage, which is suitable for fail-safe designs.
This outstanding isolation performance is superior to
alternatives including devices based on capacitive- or
magnetic-coupling with DTI in micro-meter range. Offered
in an SO-16 package, the isolated ADC delivers the reli-
ability, small size, superior isolation and over-temperature
performance motor drive designers need to accurately
measure current at much lower price compared to tradi-
tional current transducers.
The internal clock version modulators, HCPL-7860 (DIP-8/
gull wing surface mount package) and HCPL-786J (SO-16
package), are also available.
Features
5 MHz to 20 MHz external clock input range
1-bit, second-order sigma-delta modulator
16 bits resolution no missing codes (12 bits ENOB)
74 dB minimum SNR
3.5 V/°C maximum offset drift
±1% maximum gain error
Internal reference voltage
±200 mV linear range with single 5 V supply
3 V to 5.5 V wide supply range for digital interface
–40°C to +105°C operating temperature range
SO-16 package
25 kV/s common-mode transient immunity
Safety and regulatory approval:
IEC/EN/DIN EN 60747-5-5: 1414 Vpeak working
insulation voltage
UL 1577: 5000 Vrms/1min double protection rating
CSA: Component Acceptance Notice #5
Applications
Motor phase and rail current sensing
Power inverter current and voltage sensing
Industrial process control
Data acquisition systems
General purpose current and voltage sensing
Traditional current transducer replacements
Functional Block Diagram
VDD1
VIN+ Σ−Δ LED
MODULATOR/ DRIVER
DECODER
VINENCODER
SHIELD
VDD2
MDAT
GND1
VREF
CLOCK
DETECTOR
SHIELD
LED
DRIVER
ACPL-796J
MCLKIN
GND2
Figure 1.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD. The components
featured in this datasheet are not to be used in military or aerospace applications or environments.

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ACPL-796J pdf
Table 4. Insulation and Safety Related Specifications
Parameter
Minimum External Air Gap
(External Clearance)
Symbol
L(101)
Value
8.3
Minimum External Tracking
(External Creepage)
L(102)
8.3
Minimum Internal Plastic Gap
(Internal Clearance)
0.5
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
CTI
>175
IIIa
Units
mm
mm
mm
V
Conditions
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Min. Max.
Units
Storage Temperature
TS
–55 +125
°C
Ambient Operating Temperature
Supply voltage
Steady-State Input Voltage[1,3]
Two-Second Transient Input Voltage[2]
Digital Input/Output Voltages
Lead Solder Temperature
TA –40 +105
VDD1, VDD2
–0.5 6.0
VIN+, VIN
–2 VDD1 + 0.5
VIN+, VIN
–6 VDD1 + 0.5
MCLKIN, MDAT
–0.5
VDD2 + 0.5
260°C for 10 sec., 1.6 mm below seating plane
°C
V
V
V
V
Notes:
1. DC voltage of up to –2 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
2. Transient voltage of 2 seconds up to –6 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
3. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs.
Table 6. Recommended Operating Conditions
Parameter
Ambient Operating Temperature
VDD1 Supply Voltage
VDD2 Supply Voltage
Analog Input Voltage[1]
Notes:
1. Full scale signal input range ±320 mV.
Symbol
TA
VDD1
VDD2
VIN+, VIN
Min.
–40
4.5
3
–200
Max.
+105
5.5
5.5
+200
Units
°C
V
V
mV
5

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ACPL-796J arduino
Latch-up Consideration
Latch-up risk of CMOS devices needs careful consider-
ation, especially in applications with direct connection to
signal source that is subject to frequent transient noise.
The analog input structure of the ACPL-796J is designed
to be resilient to transients and surges, which are often
encountered in highly noisy application environments
such as motor drive and other power inverter systems.
Other situations could cause transient voltages to the
inputs include short circuit and overload conditions. The
ACPL-796J is tested with DC voltage of up to –2 V and 2-
second transient voltage of up to –6 V to the analog inputs
and there is no latch-up or damage to the device.
Modulator Data Output
Input signal information is contained in the modulator
output data stream, represented by the density of ones
and zeros. The density of ones is proportional to the input
signal voltage, as shown in Figure 15. A differential input
signal of 0 V ideally produces a data stream of ones 50%
of the time and zeros 50% of the time. A differential input
of –200 mV corresponds to 18.75% density of ones, and
a differential input of +200 mV is represented by 81.25%
density of ones in the data stream. A differential input of
+320 mV or higher results in ideally all ones in the data
stream, while input of –320 mV or lower will result in all
zeros ideally. Table 10 shows this relationship.
MODULATOR OUTPUT
ANALOG INPUT
Figure 15. Moudlator output vs. analog input.
+FS (ANALOG INPUT)
0 V (ANALOG INPUT)
–FS (ANALOG INPUT)
TIME
Table 10. Input voltage with ideal corresponding density of 1s at modulator data output, and ADC code.
Analog Input
Full-Scale Range
+Full-Scale
+Recommended Input Range
Voltage Input
640 mV
+320 mV
+200 mV
Density of 1s
100%
81.25%
ADC Code (16-bit unsigned decimation)
65,535
53,248
Zero
–Recommended Input Range
0 mV
–200 mV
50%
18.75%
32,768
12,288
–Full-Scale
–320 mV
0%
0
Notes:
1. With bipolar offset binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until
the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
2. Ideal density of 1s at modulator data output can be calculated with VIN/640 mV + 50%; similarly, the ADC code can be calculated with (VIN/640 mV)
× 65,536 + 32,768, assuming a 16-bit unsigned decimation filter.
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