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PDF ACPL-352J Data sheet ( Hoja de datos )
| Número de pieza | ACPL-352J | |
| Descripción | 5.0 Amp Output Current IGBT and SiC/GaN MOSFET Gate Drive Optocoupler | |
| Fabricantes | AVAGO | |
| Logotipo |  |
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ACPL-352J
5.0 Amp Output Current IGBT and SiC/GaN MOSFET Gate Drive
Optocoupler with Integrated Over Current Sensing,
FAULT, GATE and UVLO Status Feedback
Data Sheet
Description
The ACPL-352J is a 5.0A intelligent gate drive optocoupler. The
high peak output current and wide operating voltage range
make it ideal for driving IGBT or SiC/GaN MOSFET directly in
motor control and inverter applications.
The device features fast propagation delay with excellent
timing skew performance. It provides IGBT/MOSFET with over
current protection and functional safety reporting. This
full-featured and easy-to-implement gate drive optocoupler
comes in a compact, surface-mountable SO-16 package. It
provides reinforced insulation certified for safety regulatory
IEC/EN/DIN, UL and CSA.
CAUTION
It is advised that normal static precautions be
taken in handling and assembly of this
component to prevent damage and/or
degradation which may be induced by ESD. The
components featured in this data sheet are not
to be used in military or aerospace applications
or environments.
Features
5.0 A maximum peak output current
4.5 A minimum peak output current
150 ns maximum propagation delay
Dual output drive to control turning on and off time
Over current detection with configurable "Soft" shutdown
Functional Safety Reporting
— Over current FAULT feedback
— IGBT/MOSFET GATE status feedback
— UVLO status feedback
Under Voltage Lock-Out (UVLO) with Hysteresis
50 kV/μs Minimum Common Mode Rejection (CMR) at
VCM = 1500 V
15V to 30V wide operating VDD2 range
–40°C to 105°C industrial temperature range
8.3mm creepage and clearance
Safety approval:
— UL Recognized 5000 VRMS for 1min.
— CSA
— IEC/EN/DIN EN 60747-5-5 VIORM = 1414 VPEAK
Applications
IGBT and SiC/GaN MOSFET gate drive
Industrial drives and inverters
Renewable energy inverters
Switching power supplies
Avago Technologies
-1-
1 page  
ACPL-352J
Data Sheet
ACPL-352J 16-Lead Surface Mount Package
ACPL-352J 16-Lead Surface Mount Package
0.457
(0.018)
16 15 14 13 12 11 10 9
1.270
(0.050)
LAND PATTERN RECOMMENDATION
0.64 (0.025)
AVAGO
LEAD-FREE
PIN 1 DOT
A 352J
YYWW
EEE
TYPE NUMBER
DATE CODE
7.493 ± 0.254
(0.295 ± 0.010)
LOT ID
12345678
10.312 ± 0.254
(0.406 ± 0.10)
9°
8.763 ± 0.254
(0.345 ± 0.010)
11.63 (0.458)
2.16 (0.085)
ALL LEADS TO
BE COPLANAR
± 0.05 (0.002)
0.457
(0.018)
3.505 ± 0.127
(0.138 ± 0.005)
Dimensions in Millimeters (Inches)
Floating lead protrusion is 0.25 mm (10 mils) Max.
0-8°
0.64 (0.025) MIN.
10.363 ± 0.254
(0.408 ± 0.010)
0.203 ± 0.076
(0.008 ± 0.003)
STANDOFF
Note: Initial and continued variation in color of the white mold compound is normal and does not affect performance or reliability of the device
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non- Halide Flux should be used.
Regulatory Information
The ACPL-352J is approved by the following organizations.
IEC/EN/DIN EN 60747-5-5
UL
CSA
Maximum working insulation voltage VIORM = 1414VPEAK
Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361.
Approval under CSA Component Acceptance Notice #5, File CA 88324.
Avago Technologies
-5-
5 Page 
ACPL-352J
Data Sheet
Table 6. Switching Specifications (AC)
Table 6. Switching Specifications (AC)
All typical values at TA = 25°C, VDD1 = 5V, VDD2 – VS = 15 V, VS – VSS2 = 15 V; All minimum and maximum specifications are at
recommended operating conditions, unless otherwise noted.
Parameter
Symbol
Min. Typ. Max. Units Test Conditions
Fig. Note
Propagation Delay Time to High VOUTP
Output Level
Propagation Delay Time to Low VOUTN
Output Level
Pulse Width Distortion
tPLH
tPHL
PWD
40 100 150 ns
40 90 150 ns
–50 10 50 ns
RGP = 5, RGN = 5,
CG = 5nF, f = 20 kHz,
Duty Cycle = 50%
IF = 8 mA
16, 17,
22
a
b
c
Propagation Delay Difference Between PDD ( tPLH – tPHL) –75
Any Two Parts
75 ns
d
Propagation Delay Skew
tPSK
60 ns
e
10% to 90% Rise Time on VOUTP
90% to 10% Fall Time on VOUTN
tR
tF
37 ns RGP = 5, RGN = 5,
30 ns CG = 2nF, f = 20 kHz,
Duty Cycle = 50%,
IF = 8mA.
OC Blanking Time
tOC(BLANKING)
OC Detection to 90% VGATE Delay
tOC(90%)
OC Detection to VGATE=2V Delay
tOC(2V)
OC Detection to OC Pull Low Propagation tOC(LOW)
Delay
0.75 1
0.13
2.5
0.25
μs RGP = 5, RGN = 5, 21 f
μs
CG = 5 nF, f = 100 Hz,
Duty Cycle = 50%,
21
g
μs IF = 8 mA, RSS=133, 21 h
μs CF = 330 pF, RF = 10 k 21 i
OC Detection to SS Pull Low Propagation tSS(LOW)
Delay
0.15 0.8
μs
18,21 j
OC Detection to Low Level FAULT Signal tOC(FAULT)
Delay
1.7 3
μs
21 k
Output Mute Time due to Over Current tOC(MUTE)
2 3 4 ms
19, 21 l
Time Input Kept Low Before Fault Reset to tOC(RESET)
High
2 3 4 ms CF = 330 pF, RF = 10 k 19, 21 m
VDD2 to UVLO High Delay
tPLH_UVLO
15 22 μs CU = 330 pF,
RU = 10 k
23 n
VDD2 to UVLO Low Delay
tPHL_UVLO
13 30 μs CU = 330 pF,
RU = 10 k
23 o
VDD2 UVLO to VOUTP High Delay
tUVLO_ON
3 μs
23 p
VDD2 UVLO to VOUTN Low Delay
tUVLO_OFF
1.5 μs
23 q
Delay Time to VGATE Status Check
tGFAULT
7.5 9.5 13
μs
24 r
VGATE Status Check to Low Level GFAULT tGFAULT(10%)
Signal Delay
13.5 17 μs CGF =330 pF,
RGF = 10 k
24 s
Avago Technologies
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