|
|
PDF W25Q80DV Data sheet ( Hoja de datos )
| Número de pieza | W25Q80DV | |
| Descripción | 3V 8M-BIT SERIAL FLASH MEMORY | |
| Fabricantes | Winbond | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de W25Q80DV (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
W25Q80DV
3V 8M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
-1-
Publication Release Date:February 11, 2015
Preli mry-Revision F
1 page  
W25Q80DV
1. GENERAL DESCRIPTION
The W25Q80DV (8M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial
Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI
(XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with
current consumption as low as 1µA for power-down. All devices are offered in space-saving packages.
The W25Q80DV array is organized into 4,096 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80DV
has 256 erasable sectors and 16 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See figure 2.)
The W25Q80DV supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing
equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O
when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable
write protection, with top, bottom or complement array control, provide further control flexibility.
Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit
Unique Serial Number.
2. FEATURES
Family of SpiFlash Memories
– W25Q80DV: 8M-bit/1M-byte (1,048,576)
– 256-byte per programmable page
– Standard SPI: CLK,/CS,DI,DO,/WP,/Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Uniform 4KB Sectors, 32KB & 64KB Blocks
Highest Performance Serial Flash
– 104MHz Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/S continuous data transfer rate
Software and Hardware Write Protection
– Write-Protect all or portion of memory
– Enable/Disable protection with /WP pin
– Top or bottom array protection
Flexible Architecture with 4KB sectors
– Uniform Sector/Block Erase (4/32/64-kbytes)
– Program one to 256 bytes < 0.8ms
– Erase/Program Suspend & Resume
– More than 100,000 erase/write cycles
– More than 20-year data retention
Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– <1µA Power-down(typ.)
Space Efficient Packaging(1):
– 8-pin SOIC 150-mil/208mil, VSOP 150-mil
– 8-pad WSON 6x5-mm, USON 2x3-mm
– 8-pin PDIP 300-mil
– 8-ball WLCSP
– Contact Winbond for KGD and other options
Note 1. Some package types are special orders,
please contact Winbond for ordering
information.
-5-
Publication Release Date:February 11, 2015
Preli mry-Revision F
5 Page 
W25Q80DV
6. FUNCTIONAL DESCRIPTION
6.1 SPI OPERATIONS
Standard SPI Instructions
The W25Q80DV are accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge CLK.
SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0
and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and
data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling
and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising edges of
/CS.
Dual SPI Instructions
The W25Q80DV support Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast
Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal
for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-
critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins
become bidirectional I/O pins: IO0 and IO1.
Quad SPI Instructions
The W25Q80DV support Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, “Fast
Read Quad I/O (EBh)” instructions. These instructions allow data to be transferred to or from the device
six to eight times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant
improvement in random access transfer rates allowing fast code-shadowing to RAM or execution directly
from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0
and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require
the non-volatile Quad Enable bit (QE) in Status Register 2 to be set.
Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q80DV operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume
where it left off once the bus is available again. The /HOLD function is only available for standard SPI
and Dual SPI operation, not during Quad SPI.
Publication Release Date:February 11, 2015
- 11 -
Prelimry-Revision F
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W25Q80DV.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| W25Q80DV | 3V 8M-BIT SERIAL FLASH MEMORY | Winbond |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |