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PDF PEEL16V8S-25L Data sheet ( Hoja de datos )

Número de pieza PEEL16V8S-25L
Descripción CMOS Programmable Electrically Erasable Logic
Fabricantes ICT 
Logotipo ICT Logotipo



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No Preview Available ! PEEL16V8S-25L Hoja de datos, Descripción, Manual

Features
PEEL™ 16CV8 -25
CMOS Programmable Electrically Erasable Logic Device
Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super sets standard 20-pin PLDs (PALs)
General Description
The PEELTM 16CV8 is a Programmable Electrically Erasable Logic
(PEEL) device providing an attractive alternative to ordinary PLDs. The
PEELTM 16CV8 offers the performance, flexibility, ease of design and
production practicality needed by logic designers today.
The PEELTM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP
packages (see Figure 1) with 25ns speed and power consumption as low
as 37mA. EE-Reprogrammability provides the convenience of instant
reprogramming for development and reusable production inven- tory
minimizing the impact of programming changes or errors. EE-
Reprogrammability also improves factory testability, thus assuring the
highest quality possible.
Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
Development / Programmer Support
- Third party software and programmers
- Anachip WinPLACE Development Software
- Automatic programmer translation and JEDEC file translation
software available for the most popular PAL devices
The PEELTM 16CV8 architecture allows it to replace over standard 20-
pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. Anachip’s PEELTM
16CV8 can be programmed with existing 16CV8 JEDEC file. Some pro-
grammers also allow the PEELTM 16CV8 to be programmed directly
from PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional develop-
ment and programming support for the PEELTM16CV8 is provided by
popular third-party programmers and development software. Anachip
also offers free WinPLACE development software.
Figure 1 - Pin Configuration
Figure 2 - Block Diagram
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under
any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
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PEEL16V8S-25L pdf
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Figure 6 - PEEL TM 16CV8 Logic Array - Simple Mode (see Figure 3 for macrocell details)
Anachip Corp.
www.anachip.com.tw
5/11
MACRO
CELL
19 I/O
MACRO
CELL
18 I/O
MACRO
CELL
17 I/O
MACRO
CELL
16 I/O
MACRO
CELL
15 I/O
MACRO
CELL
14 I/O
MACRO
CELL
13 I/O
MACRO
CELL
12 I/O
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Rev. 1.0 Dec 16, 2004

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PEEL16V8S-25L arduino
Anachip Corp.
Head Office
,
2F, No. 24-2, Industry E. Rd. IV, Science-Based
Industrial Park, Hsinchu, 300, Taiwan
Tel: +886-3-5678234
Fax: +886-3-5678368
Anachip USA
780 Montague Expressway, #201
San Jose, CA 95131
Tel: (408) 321-9600
Fax: (408) 321-9696
Website: http://www.anachip.com
©2004 Anachip Corp.
Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by
Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip for
its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any
patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life support devices
or systems.
Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp.
Anachip Corp.
www.anachip.com.tw
11/11
Rev. 1.0 Dec 16, 2004

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