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PDF TC551001AFTL-10LV Data sheet ( Hoja de datos )

Número de pieza TC551001AFTL-10LV
Descripción SILICON GATE CMOS STATIC RAM
Fabricantes Toshiba 
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TOSHIBA
TC55100lAPL/AFL/AFlL/ATRL-70L/85L/10L(LV)
SILICON GATE CMOS
131,072 WORD x 8 BIT STATIC RAM
Description
The TC551 001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated
from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating cur-
rent of 5mAlMHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low
power standby mode in which the standby current is 2~ typically. The TC551 001APL has three control inputs. Chip enable inputs
(CE1, CE2) allow for device selection and data retention control, while an output enable input (OE) provides fast memory access.
The TC551 001 APL is suitable for use in microprocessor systems where high speed, low power, and battery backup are required.
The TC551 001 APL-L(LV) operates and is characterized at both 3 and 5 volts.
The TC551 001 APL is offered in a standard dual-in-line 32-pin plastic package, a small outline plastic package, and a thin small
outline plastic package (forward type, reverse type).
Features
Pin Connection (Top View)
• Low power dissipation:
• Standby current:
• Single 5V power supply
• Access time (max.)
27.5mW/MHz (typ.)
4~ (max.) at Ta = 25°C
TC551 001 APL/AFL/AFTL/ATRL
Access Time
CE1 Access Time
CE2 Access Time
C5E Access Time
-70L(LV)
70ns
70ns
70ns
35ns
-85L(LV)
85ns
85ns
85ns
45ns
-10L(LV)
100ns
100ns
100ns
50ns
• Power down feature:
CE1, CE2
• Data retention supply voltage:
2.0 - 5.5V
• Inputs and outputs TIL compatible
• Package
TC551 001 APL : DIP32-P-600
NC
A16
A14
A12
A7
A6
AS
A4
A3
A2
Al
AO
1/01
1102
1/03
GND
Pin Names
TC551001AFL
TC551 001 AFTL
TC551001ATRL
: SOP32-P-525
: TSOP32-P-0820
: TSOP32-P-0820A
Voo
A1S
CE2
RIW
At3
AS
A9
All
M
Aml0
1/08
1/07
1/06
1/05
1/04
032 PIN TSOP
(forward type) (reverse type)
t6 16
,.,17 32 32
AO - A16 Address Inputs
RIW
ReadlWrite Control Input
OE Output Enable Input
CE1, CE2 Chip Enable Inputs
1/01 - 1/08 Data Input/Output
Voo Power (+5V)
GND
Ground
NC No Connection
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN NAME A11 Ag As A13 RIW CE2 A15 Voo NC A16 A14 A12 A7 A6 A5 A4
PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN NAME A3 A2 A1 Ao 1/01 1/02 1/03 GND 1/04 1/05 1/06 1/07 1/08 CE1 AlO OE
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
A-99

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TC551001AFTL-10LV pdf
Timing Waveforms
Read Cycle (1)
ADDRESSES
Static RAM TC551 001 APUAFUAFTUATRL-70U85U1 OL(LV)
teo2
teo,
toe
DOUT
Write Cycle 1 (4) (RIW Controlled Write)
ADDRESSES
R/W
eE2
m
DOUT
OUTPUT DATA VALID
twc
twp tWR
DATA STABLE
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
A-103

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