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PDF TC551001APL-10 Data sheet ( Hoja de datos )

Número de pieza TC551001APL-10
Descripción SILICON GATE CMOS STATIC RAM
Fabricantes Toshiba 
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No Preview Available ! TC551001APL-10 Hoja de datos, Descripción, Manual

TOSHIBA
SILICON GATE CMOS
1nC55100lAPL/PUFL/P.U![L/l\1]{L-70/85/10OL1)
131,072 WORD x 8 BIT STATIC RAM
Description
The TC551 001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated
from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating Cur-
rent of 5mNMHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low
power standby mode in which the standby current is 2~ typically. The TC551 001 APL has three control inputs. Chip enable inputs
(CE1, CE2) allow for device selection and data retention control, while an output enable input (OE) provides fast memory access.
The TC551 001 APL is suitable for use in microprocessor systems where high speed, low power, and battery backup are required.
The TC551 001 APL-(LT) has an operating temperature range of -20 - 70DC so it is suitable for use in low temperature applications.
The TC551 001 APL is offered in a standard dual-in-line 32-pin plastic package, a small outline plastic package, and a thin small
outline plastic package (forward type, reverse type).
Features
• Low power dissipation:
• Standby current:
27.5mW/MHz (typ.)
100~(max.)
• Single 5V power supply
• Access time (max.)
TC551001APl/AFl/AFTL/ATRl
Access Time
CE1 Access Time
CE2 Access Time
OE Access Time
-70(LT)
70ns
70ns
70ns
35ns
-85(lT)
85ns
85ns
85ns
45ns
-10(lT)
100ns
100ns
100ns
50ns
• Power down feature:
CE1, CE2
• Data retention supply voltage:
2.0 - 5.5V
• Wide operating temperature:
-20 - ?ODC
• Inputs and outputs TIL compatible
• Package
TC551001APL: DIP32-P-600
Pin Names
TC551 001 AFL : SOP32-P-525
TC551001AFTL : TSOP32-P-0820
TC551 001 ATRL : TSOP32-P-0820A
AO - A16 Address Inputs
RIW
ReadIWrite Control Input
OE Output Enable Input
CE1, CE2 Chip Enable Inputs
1/01 - 1/08 Data Input/Output
Voo
GND
Power (+5V)
Ground
NC No Connection
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN NAME A11 Ag As A 13 RIW CE2 A15 Voo NC A16 A14 A12 A7 A6 A5 A4
PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN NAME A3 A2 A1 Ao 1/01 1/02 1/03 GND 1/04 1/05 1/06 1/07 1/08 CE1 A10 OE
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
A-S3

1 page




TC551001APL-10 pdf
Timing Waveforms
Read Cycle (1)
ADDRESSES
Static RAM
TC551001APUAFUAFTUATRL-70/85/10(LT)
DOUT ------4------;c:;
OUTPUT DATA VALID
Write Cycle 1 (4) (RIW Controlled Write)
ADDRESSES
twc
twp tWR
DATA STABLE
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
A-87

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