PDF MT6167 Data sheet ( Hoja de datos )

Número de pieza	MT6167
Descripción	RF System
Fabricantes	MediaTek
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1. MT6167 pdf mediatek Hay una vista previa y un enlace de descarga de MT6167 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! MT6167 RF System Datasheet Version: Release date/Status: Editor: 1.1 2012/11/15 Chi-Yao Yu © 2012 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. [email protected],time=2013-01-20 00:44:07,ip=125.77.137.19,doctitle=MT6167 Datasheet V1p1.pdf,company=Lenovo_WCX 1 page MT6167 Datasheet Confidential A SWITCHPLEXER ANT Decoder VCCD_ 2.8VDC VCONT1 VCONT2 VCONT3 VCONT4 B1 / B4 B2 / PCS1900 LNA_5P LNA_5N LNA LNA_3P LNA_3N LNA DCS1800 LNA_1P HBSEL B8 / GSM900 LNA_1N LNA_2P LNA_2N B5 / GSM850 LNA_4P LNA_4N LNA LNA LNA LBSEL B1/B4 LNA_D3P LNA ANT LNA_D3N DRX LNA_D1P LNA B2 LNA_D1N LNA_D2P B5 / B8 LNA_D2N CLK_SEL CLK4 LNA CLK3 CLK2 ½ ½ ½ ¼ ½ ½ ¼ ½ XTAL1 / REFIN AFCDAC VCC_PA PA_bias PDET WCDMA PA Module B4 VMODE PAEN BANDSEL VCC_PA PA_bias PDET PDET VBAT HB WCDMA PA Module LB VMODE PAEN BANDSEL HB GSM/EDGE PA Module LB VTCXO V28 VRT VXODIG VIO18 VTXHF2 VTXHF1 VRXHF VLF2 VLF1 TXBPI1 TMEAS TX_PDET TX_HB3 TX_HB2 TX_HB1 TX_LB1 TX_LB2 VRAMP VMODE PAEN BANDSEL TX Cal 1/2 1/4 Figure 2 : Applications Diagram DAC DAC DAC DAC Divider SDM RCAL EN_BB CLK1 DCXO_32K XMODE VCORE BSI [4:0] Version 1.1 © MediaTek Inc. 15-Nov-12 Page 5 of 39 [email protected],time=2013-01-20 00:44:07,ip=125.77.137.19,doctitle=MT6167 Datasheet V1p1.pdf,company=Lenovo_WCX 5 Page 3.5 Operating Conditions Within the operating range the IC operates as per the functional description. Parameter Conditions Min Nom Max Unit Supply VIO18 1.7 1.8 1.9 V SMPS Supply VRF18 1.75 1.825 1.9 V Linear Supply VTCXO28 2.7 2.8 2.9 V Supply VXODIG Normal function mode Connects to VIO18 Supply VXODIG Supply VXODIG 32K-less mode ATPG mode – LDO’s bypassed in this mode Connects to VTCXO28 1.1 1.2 1.4 V Receiver Front End RX input frequency range See Receiver Section for detailed frequency ranges Rx required amplitude balance All Rx input pairs -1 +1 dB Rx required phase balance All Rx input pairs -10 +10 deg Transmitter Tx Frequency Range Tx O/P VSWR See Transmitter Section for detailed frequency ranges All Phases ZL = 50Ω 2:1 Clock Buffers CLK1, CLK2,CLK3 Load (Rload\|\|Cload) to GND Cload Rload See section [7.3] pF k Reference Clock Input (VCTCXO) Reference Clock Frequency 26.0 MHz Reference Clock Input Voltage Swing AC coupled at input pin 700 1500 mVpp Duty Cycle 40 60 % Phase Noise – note 2 @ Foffset = 100Hz @ Foffset = 1KHz @ Foffset = 10KHz @ Foffset = 100KHz HD2 @ 52MHz <-103 <-133 <-147 <-149 -100 -130 -144 -146 -8 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc HD3 @ 78MHz -10 dBc Harmonic Content Start-up time HD4 @ 104MHz \|Δf\|<1ppm to >90% of final amplitude -20 dBc 3 ms Crystal Requirements 2 Crystal types are supported (Crystal #1 3225 body size / Crystal #2 2520 body size) Crystal #1 7.5 pF Nominal Load Capacitance Crystal #2 7.0 pF Initial Frequency error ±10 Ppm ESR Drive level 30  100 μW Crystal #1 -10% 32 +10% ppm/pF Pullability Crystal #2 -10% 27 +10% ppm/pF Note 1 Version 1.2 (draft) [email protected],time=2013-01-20 00:44:07,ip=125.77.137.19,doctitle=MT6167 Datasheet V1p1.pdf,company=Lenovo_WCX © MediaTek Inc. 2012-11-15 11 Page

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