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PDF TC51864PL-85 Data sheet ( Hoja de datos )

Número de pieza TC51864PL-85
Descripción SILICON GATE CMOS PSEUDO STATIC RAM
Fabricantes Toshiba 
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No Preview Available ! TC51864PL-85 Hoja de datos, Descripción, Manual

TOSHIBA
SILICON GATE CMOS
65,536 WORD x 8 BIT CMOS PSEUDO STATIC RAM
1l:51864PL/FL~5/10
PRELIMINARY
Description
The TC51864PL is a 512K bit high speed CMOS pseudo static RAM organized as 65,536 words by 8 bits. The TC51864PL utilizes
a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power storage. The
TC51864PL operates from a single 5V power supply. Refreshing is supported by a refresh (RFSH) input which enables two types of
refreshing - auto refresh and self refresh. The TC51864PL features a static RAM-like interface with a write cycle in which the input
data is written into the memory cell at the rising edge of RNV thus simplifying the microprocessor interface.
The TC51864PL is available in a 32-pin, 0.6 inch width plastic DIP, and a small outline plastic flat package.
Features
• Organization: 65,536 words x 8 bits
• Single 5V power supply
• Fast access time
TC51864 Family
-85 -10
tCEA CE Access Time
tOEA OE Access Time
tRC Cycle Time
Power Dissipation
Self Refresh Current
85ns
100ns
35ns
40ns
135ns
160ns
385mW 330mW
100J,LA
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Inputs and outputs TIL compatible
• Refresh: 256 refresh cycles/4ms
• Package
- TC51864PL: DIP32-P-600
- TC51864FL: SOP32-P-525
Pin Names
AO - A15
Address Inputs
RIW
Read/Write Control Input
OE Output Enable Input
RFSH
Refresh Input
CE Chip Enable Input
CS Chip Select Input
1/01 -1/08 Data Inputs/Outputs
Voo
GND
Power
Ground
NC No Connect
Pin Connection (Top View)
RFSH
NC
A14
A12
A7
A6
AS
A4
A3
A2
Al
AO
1/01
1102
1/03
GNO
Voo
A15
CS
RIW
A13
A8
A9
A 11
OE
A10
CE
1108
1107
1106
'1105
1104
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
D-9

1 page




TC51864PL-85 pdf
Static RAM
TC51864PUFL-85/10
Notes:
1) Stress greater than those listed under "Maximum Ratings" may cause permanent damage to the device.
2) All voltages are referenced to GND.
3) 1000 depends on the cycle time.
4) 1000 depends on the output loading. Specified values are obtained with the outputs open.
5) An initial pause of 100j.lS with high CE is required after power-up before proper device operation is achieved.
6) AC measurements assume tT =5ns.
7) Timing reference levels
Input Levels
Input Reference Levels
Output Reference Levels
V1H = 2.6V INPUT
V1L = 0.6V
2.6V--"'\.1~'!":"'!""---­
O.6V
V1H = 2.4V
V1L = 0.8V
VOH = 2.2V
VOL = 0.8V
OUTPUT
INPUT REFERENCE
LEVEL
2.2V
OUTPUT REFERENCE
LEVEL
8) Measured with a load equivalent to 1 TIL load and 100pF.
9) tCHZ' toHZ' tWHz define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
10) For write cycles, the input data is latched at the earlier of Am or CE rising edge. Therefore, the input data must be valid
during the setup time (tosw or tosd and hold time (tOHW or tOHd.
11) All address inputs are latched at the falling edge of CEo Therefore, all the address inputs must be valid during ~sc and tAHc.
12) The two refresh operations, auto refresh and self refresh, are defined by the RFSH pulse width under the condition CE =V1H.
Auto refresh : RFSH pulse width::; tFAP (max.)
Self refresh : RFSH pulse width ~ tFAS (min.)
The timing parameter tFRS must be met for proper device operation under the following conditions:
• after self refresh
• if RFSH = "L" after power-up
13) CE only refresh or auto refresh must begin within 15.6j.lS after self refreshing ends.
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
0-13

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