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PDF TC55BS4258J-12 Data sheet ( Hoja de datos )

Número de pieza TC55BS4258J-12
Descripción 256K x 4-Bit Synchronous Static RAM
Fabricantes Toshiba 
Logotipo Toshiba Logotipo



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No Preview Available ! TC55BS4258J-12 Hoja de datos, Descripción, Manual

TOSHIBA
262,144 WORD x 4 BIT SYNCHRONOUS STATIC RAM
with Input Registers, Output Registers and Pass-Through Feature
1l:55BS4258]-10/12
PRELIMINARY
Description
The TC55BS4258J is a 1,048,576 bit synchronous static random access memory fabricated using BiCMOS technology and
organized as 262,144 words by 4 bits. The TC55BS4258J has separate data inputs and outputs and a write-cycle pass-through
feature.
Designed for pipelined architectures, this device has internal input and output registers which latch on the positive edge
of an external clock (ClK). All address, data, and control signals are latched. The setup and hold times for the inputs are 2ns
and 1ns respectively. Synchronous SRAMs can lead to faster, more robust system operation by virtually eliminating the timing
skew problems associated with conventional asynchronous SRAMs. For example, write operations are internally self-timed
when initiated - eliminating the need for accurate write pulse generation and timing by the memory controller or microproces-
sor. A pass-through feature during write cycles allows the outputs to follow the inputs with a one clock cycle delay. For read
cycles, data is available one clock cycle after the address is latched. All inputs and outputs are TIL compatible.
The TC55BS4258J is available in a 36-pin, 400mil SOJ package suitable for high density assembly.
Features
• Fast cycle time
- TC55BS4258J-10 10ns (max.)
- TC55BS4258J-12 12ns (max.)
• Fast clock access time
- TC55BS4258J-10 5ns (max.)
- TC55BS4258J-12 6ns (max.)
• Input and output registers for synchronous operation
• Data pass-through for write cycles
• Single power supply: 5V ± 10%
• Separate data inputs and outputs
• Package: JEDEC standard pinout
- 36-pin, 400mil SOJ: SOJ36-P-400
Pin Names
AD - A17
DO - D3
00-03
ClK
CE
WE
OE
Voo
GND
NC
Address Inputs
Data Inputs
Data Outputs
Clock Input
Chip Enable Input
Write Enable Input
Output Enable Input
Power (+5V)
Ground
No Connection
Pin Connection (Top View)
TC55BS425BJ
NC
A3
A2
A1
AO
CE
DO
QO
VDD
GND
Q1
01
WE
A17
A16
A1S
A14
NC
A4
AS
A6
A7
AS
Of
03
Q3
GND
VDD
Q2
02
CLK
A9
A10
A11
A12
At3
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
C-1

1 page




TC55BS4258J-12 pdf
Timing Waveforms
Read Cycle 1 (OE = Vn)
Standby
Static RAM
Read Read
TC55BS4258J-10112
Read
Read Cycle 2 (CE = V1J
Read
Output Disable
Read
Read
PRELIMINARY
tACK
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
C-5

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