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PDF FM8PE55 Data sheet ( Hoja de datos )
| Número de pieza | FM8PE55 | |
| Descripción | EPROM/ROM-Based 8-Bit Microcontroller | |
| Fabricantes | Feeling Technology | |
| Logotipo |  |
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FEELING
TECHNOLOGY
FM8PE55/E57
EPROM/ROM-Based 8-Bit Microcontroller Series
Devices Included in this Data Sheet:
‧ FM8PE55E/E57E : EPROM devices
‧ FM8PE55/E57 : Mask ROM devices
FEATURES
‧ Only 47 single word instructions
‧ All instructions are single cycle except for program branches which are two-cycle
‧ 13-bit wide instructions
‧ All ROM/EPROM area GOTO/FGOTO instruction
‧ All ROM/EPROM area subroutine CALL/FCALL instruction
‧ 8-bit wide data path
‧ 5-level deep hardware stack
‧ Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
Pins # I/O # EPROM/ROM (Word) RAM (Byte)
FM8PE55/E55E 28
20
512
48
FM8PE57/E57E 28
20
2K
96
‧ Direct, indirect addressing modes for data accessing
‧ 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
‧ Internal Power-on Reset (POR)
‧ Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
‧ Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
‧ On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
‧ Three I/O ports IOA, IOB and IOC with independent direction control
‧ 16 soft-ware control pull-high pins: Port B/Port C
‧ 8 soft-ware control pull-down pins:IOA0~A3/IOB0~B3
‧ 2 soft-ware control open-drain pins: IOC6/IOC7
‧ One internal interrupt source: Timer0 overflow; One external interrupt source: INT pin
‧ Wake-up from SLEEP by Port B/IOC4/IOC5 input falling
‧ Power saving SLEEP mode
‧ Programmable Code Protection
‧ Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- XT: Crystal/Resonator Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
‧ Wide-operating voltage range:
- EPROM : 2.3V to 5.5V
- ROM : 2.3V to 5.5V
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Rev1.5 May 21, 2010
P.1/FM8PE55/E57
1 page  
FEELING
TECHNOLOGY
FM8PE55/E57
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the
operation of the device.
In FM8PE57/E57E, the data memory is partitioned into four banks. Switching between these banks requires the
RP1 and RP0 bits in the FSR register to be configured for the desired bank. User can use “BANK” instruction to
change the data memory bank.
TABLE 1.1: Registers File Map for FM8PE57/E57E Series
FSR<7:6>
Description
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
00
Bank 0
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCON
WUCON
PCHBUF
PDCON
BPHCON
CPHCON
INTEN
INTFLAG
01
Bank 1
10
Bank 2
11
Bank 3
Memory back to address in Bank 0
10h General
| Purpose
2Fh Registers
N/A OPTION
05h IOSTA
06h IOSTB
07h IOSTC
30h
General
General
General
General
|
Purpose
Purpose
Purpose
Purpose
3Fh
Registers
Registers
Registers
Registers
Rev1.5 May 21, 2010
P.5/FM8PE55/E57
5 Page 
FEELING
TECHNOLOGY
FM8PE55/E57
2.1.4 STATUS (Status Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
03h (r/w) STATUS GP2
GP1
GP0
TO
PD
Z
DC
C
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits
are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the
STATUS Register as 000u u1uu (where u = unchanged).
C : Carry/borrow bit.
ADDAR, ADDIA
= 1, a carry occurred.
= 0, a carry did not occur.
SUBAR, SUBIA
= 1, a borrow did not occur.
= 0, a borrow occurred.
Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)
instructions, this bit is loaded with either the high or low order bit of the source register.
DC : Half carry/half borrow bit.
ADDAR, ADDIA
= 1, a carry from the 4th low order bit of the result occurred.
= 0, a carry from the 4th low order bit of the result did not occur.
SUBAR, SUBIA
= 1, a borrow from the 4th low order bit of the result did not occur.
= 0, a borrow from the 4th low order bit of the result occurred.
Z : Zero bit.
= 1, the result of a logic operation is zero.
= 0, the result of a logic operation is not zero.
PD : Power down flag bit.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
TO : Time overflow flag bit.
= 1, after power-up or by the CLRWDT or SLEEP instruction.
= 0, a watch-dog time overflow occurred.
GP2:GP0 : General purpose read/write bits.
2.1.5 FSR (Indirect Data Memory Address Pointer)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
04h (r/w)
FSR
RP1 RP0
Indirect data memory address pointer
Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
RP1:RP0 : For FM8PE55/E55E, these bits are not used. Read as “1”s.
For FM8PE57/E57E, these bits are used to switching the bank of four data memory banks. User can use
“BANK” instruction to change bank. See 2.1.1 for detail description.
Rev1.5 May 21, 2010
P.11/FM8PE55/E57
11 Page | ||
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