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PDF FM8PE68B Data sheet ( Hoja de datos )
| Número de pieza | FM8PE68B | |
| Descripción | OTP-Based 8-Bit Microcontroller | |
| Fabricantes | Feeling Technology | |
| Logotipo |  |
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FEELING
TECHNOLOGY
FM8PE68B
OTP-Based 8-Bit Microcontroller with LCD Driver
Devices Included in this Data Sheet:
FM8PE68BA/BB: 64-pin OTP device
FM8PE68BC: 44-pin OTP device
FEATURES
Only 49 single word instructions.
4K Word on chip OTP.
All OTP area GOTO/FGOTO instruction.
All OTP area subroutine CALL/FCALL instruction.
Totally 272 x 8 bits on chip general purpose registers (SRAM):
- 144 bytes general purpose register.
- 128 bytes on-chip data RAM.
8-level deep hardware stack.
Direct, indirect addressing modes for data accessing.
One 8-bit real time clock/counter (Timer0) with 8-bit programmable pre-scaler.
Four sets of 8-bit auto reload counter/timer can be used as IROUT/PWM generator or interrupt sources:
- Counter 1: independent counter.
- Counter 2: High Pulse Width Timer, and Low Pulse Width Timer shared with IR function.
One IROUT/PWM generator.
LCD driver with 4(common) x 32(segment) pixels; 1/3, 1/2 bias and 1/4, 1/3, 1/2 duty selection.
3 channels of 15-bit resolution Resistor to Frequency Converter (RFC) output.
Internal Power-on Reset (POR).
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR).
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST).
On chip Watchdog Timer (WDT) with internal oscillator and soft-ware watch-dog enable/disable control.
Four I/O ports PORTA, PORTB, PORTC and PORTD with independent direction control.
Two output only ports PORTE and PORTF.
Soft-ware I/O pull-high/pull-down or open-drain control.
Seven internal interrupt source: Timer0, Counter1, Counter2, High-pulse width timer, Low-pulse width timer, RFC
and Fs divider; Three external interrupt source: INT0 pin, INT1 pin and Port B / Port D input status change.
Wake-up from SLEEP/IDLE by Port B/Port D input change.
Operation modes:
- Normal mode: CPU operate on high frequency main-oscillator.
- Green mode: CPU operate on low frequency sub-oscillator.
- Idle mode: CPU idle, LCD display remains working.
- Sleep mode: whole chip stop working.
Dual clock Operation: main-oscillator and sub-oscillator.
Selectable main-oscillator options:
- ERIC: External Resistor/Internal Capacitor Oscillator.
- XT: Crystal/Resonator Oscillator.
- LF: Low Frequency Crystal/Resonator Oscillator.
- PLL: Phase lock loop.
Selectable sub-oscillator options:
- ERIC: External Resistor/Internal Capacitor Oscillator.
- LF: Low Frequency Crystal Oscillator.
Wide-operating voltage range:
- OTP: 2.3V to 5.5V.
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Web site: http://www.feeling-tech.com.tw
Rev 1.00.012 Feb 17, 2016
Page 1 of 81, FM8PE68B
1 page  
FEELING
TECHNOLOGY
PIN DESCRIPTIONS
FM8PE68B
Name
I/O
Description
IOA4/INT0
I/O
Bi-direction I/O pin.
External interrupt input 0, the trigger edge is controlled by INT0EDG bit.
IOA5/INT1
I/O
Bi-direction I/O pin.
External interrupt input 1 with falling edge trigger.
IOA6/T0CKI
I/O
Bi-direction I/O pin.
Clock input to Timer0.
IOA7/IROUT
I/O
Bi-direction I/O pin.
IR mode output pin.
IOB0 ~ IOB7 I/O Bi-direction I/O port with system wake-up function.
IOC0 ~ IOC7 I/O Bi-direction I/O port.
IOD0 ~ IOD7 I/O Bi-direction I/O port with system wake-up function.
IOE0 ~ IOE7 O Output only pins.
IOF0 ~ IOF7 O Output only pins.
COM0 ~ COM3 O LCD common output pins.
SEG0 ~ SEG31 O LCD segment output pins.
VLCD1
- One of LCD bias voltage.
VLCD2
- One of LCD bias voltage.
CUP1
- Connect capacitors for LCD bias voltage.
CUP2
- Connect capacitors for LCD bias voltage.
RFC0 ~ RFC2 O The RC oscillator network output of RFC module
CX I The RC oscillator network input of RFC module
RSTB
I System clear (RESET) input. This pin is an active low RESET to the device.
Main Oscillator:
OSCI
I
- X’tal type: Oscillator crystal input.
- ERIC type: Clock input of RC oscillator.
- PLL type: Connect 0.01uF capacitor to VSS.
Main Oscillator:
OSCO
O - X’tal type: Oscillator crystal output.
-ERIC and PLL type: Instruction clock output.
Sub-Oscillator:
XIN I - X’tal type: 32.768KHZ Oscillator crystal input.
- ERIC type: Clock input of RC oscillator.
Sub-Oscillator:
XOUT
O - X’tal type: 32.768KHZ Oscillator crystal output.
- ERIC type: Instruction clock output.
VDD - Positive supply
VSS - Ground
Legend: I=input, O=output, I/O=input/output
Web site: http://www.feeling-tech.com.tw
Rev 1.00.012 Feb 17, 2016
Page 5 of 81, FM8PE68B
5 Page 
FEELING
TECHNOLOGY
2.1.2 TMR0 (Time Clock/Counter register)
FM8PE68B
Read/Write-POR
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Address
Name
B7
B6
B5
B4
B3
B2
0x01
TMR0
8-bit real-time clock/counter
Note: more bits default state, please refer to Table 2.9.
R/W-0
B1
R/W-0
B0
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an
external clock source (T0CKI pin) defined by T0CS bit (T0CON<5>). If T0CKI pin is selected, the Timer0 is increased
by T0CKI signal rising/falling edge (selected by T0SE bit (T0CON<4>)).
Please note, the pre-scaler will be cleared when TMR0 register is written with a value.
2.1.3 PCL (Low Bytes of Program Counter) & Stack
Read/Write-POR
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Address
Name
B7
B6
B5
B4
B3
0x02
PCL
Low order 8 bits of PC
Note: more bits default state, please refer to Table 2.9.
R/W-0
B2
R/W-0
B1
R/W-0
B0
FM8PE68B devices have a 12-bit wide Program Counter (PC) and eight-level deep 12-bit hardware push/pop stack.
The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called
the PCH register. This register contains the PC<11:8> bits and is not directly readable or writable. All updates to the
PCH register go through the PG<1:0> bits (STATUS<6:5>). As a program instruction is executed, the Program
Counter will contain the address of the next program instruction to be executed. The PC value is increased by one,
every instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PC<11:10> is updated from
the PG<1:0> bits (STATUS<6:5>). The PCL register is mapped to PC<7:0>.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The PC<11:10> is updated from the
PG<1:0> bits (STATUS<6:5>). The next PC will be loaded (PUSHed) into the top of STACK. The PCL register is
mapped to PC<7:0>.
For a FGOTO instruction, the PC<11:0> is provided by the FGOTO instruction word. The PCL register is mapped
to PC<7:0>, and the PG<1:0> bits is also updated from the FGOTO instruction word.
For a FCALL instruction, the PC<11:0> is provided by the FCALL instruction word. The next PC will be loaded
(PUSHed) onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PG<1:0> bits is also updated
from the FCALL instruction word.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>.
For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU result,
and the PC<9:8> will be not changed. The PG<1:0> bits whether to update to the PC<11:10>, It can be decision by
configure-word PCHS bit.
Web site: http://www.feeling-tech.com.tw
Rev 1.00.012 Feb 17, 2016
Page 11 of 81, FM8PE68B
11 Page | ||
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