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PDF FM8PU83M Data sheet ( Hoja de datos )
| Número de pieza | FM8PU83M | |
| Descripción | Full-Speed USB Controller | |
| Fabricantes | Feeling Technology | |
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遠翔科技
Feeling Technology
FM8PU83M
FM8PU83M
Full-Speed USB Controller
Datasheet R1_03.004B
March 24 2015
The datasheet contains new product information. Feeling Technology reveres
the rights to modify the product specification without notice
No liability is assumed as a result of the use of this product. No rights under any
patent accompany the sales of the product.
P.1 R1_03.004B Mar 24, 2015
FM8PU83M
1 page  
遠翔科技
Feeling Technology
FM8PU83M
5.0 Pin Description
PIN
Name
I/O
20-pin
D
1,2,
3,4
IOA[7:0] IO
17,
18,
19,
20,
IOB4
5,
IOB6
IOB1
IO
6,
16,
IOB2
15,
VSS
G
7
VREG O
8
VPP
I
9
IOB5
I
XOUT O
10
IOB3 I/O
VCC
P
12
DN
IO
IO
13
DP
IO
IO
14
OVDD P
11
Description
GPIO Port A capable of sinking up to 50 mA/pin, or sinking controlled low
or high programmable current. Can also source 2 mA current, provide a
resistive pull-up, or serve as a high-impedance input.
Use IOA7~4 in SPI mode.
GPIO Port B capable of sinking up to 50 mA/pin, or sinking controlled low
or high programmable current. Can also source 2 mA current, provide a
resistive pull-up, or serve as a high-impedance input.
Ground
3.3V Regulator output
Programming voltage supply, VCC for normal operation or IOB5 input
(pull_high)
24MHz or 16MHz or 12MHz internal oscillator output;
Or
GPIO (Default is pull-high input)
Voltage supply
USB differential data lines (D-)
IOC0
USB differential data lines (D+)
IOC1
I/O pad power Voltage supply 1.8 ~ 5.5V
Note
6.0 Program Memory Mapping
After Reset
12-bits - PC[11:0]
0000 Program execution starts here after reset
0003 The interrupt vector is fixed at 0x0003
Stack 0
Stack 1
Stack 2
CSotancFkig32
Stack 4
Stack 5
Stack 6
Stack 7
07FF
0800
0FEF
ROM-Bank=0
(2KX14)
ROM-Bank=1
(2KX14)
The FM8PU83M has program memory size greater 2K works, but the CALL and GOTO instructions only have a
11-bits address range. This 11-bit address range allows a branch within a 2K program memory page size. To allow
CALL and GOTO instructions to address the entire 4K program memory address range for FM8U83M, there is
another two bits to specify the program memory page. The paging bit comes from the ROMBANK bit (PUMODE[5]).
When doing a CALL or GOTO instruction, the user must ensure that page bit ROMBANK are programmed so that
the desired program memory page is addressed. When one of return instructions is executed, the entire 12-bit PC is
POPed from the stack. Therefore, manipulation of the ROMBANK is not required for return instructions.
P.5 R1_03.004B Mar 24, 2015
FM8PU83M
5 Page 
遠翔科技
Feeling Technology
FM8PU83M
Address 00H: Indirect Addressing Register (INDF)
Bits Description
7~0 Uses contents of FSR to address data memory
Read Write Default
Yes Yes 00h
Address 01H: Timer0 (TMR0)
Bits Description
7~0 Timer 0
Read Write Default
Yes Yes 00h
Address 02H: Low bytes of Program Counter (PCL)
Bits Description
7~0 Low bytes of Program Counter(7~0)
Read Write Default
Yes Yes 00h
Address 03H: Status Register (STATUS)
Bits Name
Description
7~5 --
Unimplemented, read as ‘0’.
4 /TO
WDT overflow flag bit (0: active)
3 /PD
Power down flag bit (0: active)
2Z
Zero flag
1 DC
Decimal carry flag or decimal/borrow flag
0C
Carry flag or/borrow flag
Read
Yes
Yes
Yes
Yes
Yes
Yes
Write
No
No
No
Yes
Yes
Yes
Default
0
1
1
0
0
0
Address 04H: File select Register (FSR)
Bits Name
Description
Read
7 --
Unimplemented, read as ‘0’.
Yes
6~0 FSR[6:0]
File select register to define address in indirect addressing mode Yes
Write Default
No 0
Yes 0
Address 05H: Port A (PORTA)
Bits Name
Description
7~0 IOA[7:0]
Port A data input/output
Read Write Default
Yes Yes 00h
Address 06H: Port B (PORTB)
Bits Name
Description
7~0 IOB[7:0]
Port B data input/output
Read Write Default
Yes Yes 00h
Address 07H: Port C (PORTC)
Bits Name
Description
7~2 --
Unimplemented, read as ‘0’.
1 IOC1
D+
The state of the D+ pins can be read at Port C data register.
0 IOC0
D-
The state of the D- pins can be read at Port C data register.
Read Write Default
Yes No 00h
Yes Yes 1
Yes Yes 1
Address 08H: Power Control Register (PCON)
Bits Name
Description
Read
7 WDTE
Watch-dog timer enable (0:disable,1:enable)
Yes
6 WDTSL
Watch-dog timer out select.
Yes
1: If Watch-dog timer out, the Device be reset.
0: If Watch-dog timer out, Device only SUSPMD (12.7H) be clear.
5~3 WDTPS[2:0] WDT prescaler
Yes
2 LVR
0: When LVDT is high or low, Device still normal work.
Yes
1: When LVDT is low, Device will be cleared SUSPEN (12.7H) bit
by H/W.
Write Default
Yes 1
Yes 1
Yes 0h
Yes 1
P.11
R1_03.004B Mar 24, 2015
FM8PU83M
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FM8PU83M.PDF ] | |
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