|
|
PDF TC58DVM92A5TA00 Data sheet ( Hoja de datos )
| Número de pieza | TC58DVM92A5TA00 | |
| Descripción | 512M-BIT (64M x 8 BITS) CMOS NAND E2PROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TC58DVM92A5TA00 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
TC58DVM92A5TA00
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M × 8 BITS) CMOS NAND E2PROM
DESCRIPTION
The device is a single 3.3 V 512Mbit (553,648,128 bit) NAND Electrically Erasable and Programmable Read-Only
Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte static
register which allows program and read data to be transferred between the register and the memory cell array in
528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes ×
32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell allay 528 × 128K × 8
Register
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read
• Mode control
Serial input/output
Command control
• Power supply
VCC = 2.7 V to 3.6 V
• Access time
Cell array to register 25 μs max
Serial Read Cycle 40 ns min
• Program/Erase time
Auto Page Program 300 μs/page typ.
Auto Block Erase 2.5 ms/block typ.
• Operating current
Read (40 ns cycle)
Program (avg.)
Erase (avg.)
Standby
20 mA max.
20 mA max.
20 mA max.
50 μA max
• Package
TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)
1 2010-07-13
1 page  
TC58DVM92A5TA00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0° to 70°C, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tWW
tRR
tRP
tRC
tREA
tCEA
tCLR
tALEA
tCEH
tOH
tRHZ
tCHZ
tREH
tIR
tWHC
tWHR
tR
tWB
tAR2
tRB
tCRY
CLE Setup Time (*1)
CLE Hold Time
CE Setup Time (*2)
CE Hold Time
Write Pulse Width
ALE Setup Time (*1)
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time (Serial Data Access)
CE Access Time (Serial Data Access)
CLE Low to RE Low
ALE Access Time (ID Read)
CE High Time for Last Address in Serial Read Cycle
Data Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
WE High to CE Low
WE High to RE Low
Memory Cell Array to Starting Address
WE High to Busy
ALE Low to RE Low (Read Cycle)
RE Last Clock Rising Edge to Busy (in Sequential Read)
CE High to Ready (When interrupted by CE in Read Mode)
tRST Device Reset Time (Ready/Read/Program/Erase)
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 10ns.
MIN
MAX
UNIT
20 ⎯
10 ⎯
30 ⎯
10 ⎯
20 ⎯
20 ⎯
10 ⎯
20 ⎯
5⎯
40 ⎯
15 ⎯
100 ⎯
20 ⎯
20 ⎯
40 ⎯
⎯ 30
⎯ 35
10 ⎯
⎯ 40
100 ⎯
10 ⎯
⎯ 30
⎯ 20
15 ⎯
0⎯
30 ⎯
30 ⎯
⎯ 25
⎯ 100
10 ⎯
⎯ 130
⎯5
⎯ 5 / 5 / 10 /
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
μs
μs
NOTES
(2)
(1) (2)
5 2010-07-13
5 Page 
Read Cycle (2) Timing Diagram
CLE
CE
tCLS tCLH
tCS tCH
TC58DVM92A5TA00
WE
tALH
tALS
tALH
ALE
RE
tDS tDH
I/O 01h
RY/BY
tR
tDS tDH
tWB
A0 to A7
A9
to A16
Column address
N*
A17
to A24
A25
*: Read operation using 01h command N: 0 to 255
tAR2
tRR tRC
tREA
DOUT
DOUT
DOUT
256 + N 256 + N + 1 527
: VIH or VIL
Read Cycle (3) Timing Diagram
CLE
CE
tCLS tCLH
tCS tCH
WE
tALH
tALS
tALH
ALE
RE
tDS tDH
I/O 50h
RY/BY
tR
tDS tDH
tWB
A0 to A7
A9
to A16
Column address
N*
A17
to A24
A25
*: Read operation using 50h command N: 0 to 15
11
tAR2
tRR tRC
tREA
DOUT
DOUT
DOUT
512 + N 512 + N + 1 527
: VIH or VIL
2010-07-13
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TC58DVM92A5TA00.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TC58DVM92A5TA00 | 512M-BIT (64M x 8 BITS) CMOS NAND E2PROM | Toshiba |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |