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PDF TC51V8512ATR-15 Data sheet ( Hoja de datos )
| Número de pieza | TC51V8512ATR-15 | |
| Descripción | SILICON GATE CMOS PSEUDO STATIC RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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rOSHIBA
SILICON GATE CMOS
TC51V8512AF/ AFT/ A1R-12/15
PRELIMINARY
524,288 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC51V8512AF is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits. The TC51V8512AF
utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high s~ed and low power
storage. The TC51 V8512AF operates from a single 3.0V power supply. Refreshing is supported by a refresh (OEIRFSH) input which
enables two types of refreshing - auto refresh and self refresh. The TC51V8512AF features a static RAM-like interface with a write
cycle in which the input data is written into the memory cell at the rising edge of RIW thus simplifying the microprocessor interface.
The TC51V8512AF is available in a 32-pin small outline plastic flat package, and a thin small outline package (forward type,
reverse type).
Features
• Organization: 524,288 words x 8 bits
• Low voltage function: 3.0V±10%
• Data retention supply voltage: 2.0V - 3.3V
• Fast access time
TC51V8512AF Family
tCEA CE Access Time
tOEA OE Access Time
tRC Cycle Time
Power Dissipation
Self Refresh Current
1 3.0V
-12 -15
120ns
150ns
60ns
80ns
190ns
230ns
99mW
66mW
40llA
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Inputs and outputs TIL compatible
• Refresh: 2048 refresh cycles/32ms
• Package
- TC51V8512AF: SOP32-P-525
- TC51V8512AFT: TSOP32-P-400
- TC518V512ATR: TSOP32-P-400A
AIS
Al6
A14
Al2
A7
A6
AS
A4
A3
A2
Al
AO
1/01
1/02
1/03
GND
Vao
AI5
AI7
Rf'N
Al3
AS
A9
All
()tJmH
AtO
ct
1108
1/07
1106
1/05
1/04
AIS
Al6
AI4
Al2
A7
A6
AS
A4
A3
A2
Al
AO
1/01
1102
1103
GND
Pin Names
AO - A18
RIW
OE/RFSH
CE
1101 - 1/08
Voo
GND
Address Inputs
Read/Write Control Input
Output Enable Input
Refresh Input
Chip Enable Input
Data InputslOutputs
Power
Ground
TDSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
D~205
1 page  
Static RAM
TC51 V8512AF/AFT/ATR·12115
Notes:
1) Stress greater than those listed under "Maximum Ratings" may cause permanent damage to the device.
2) All voltages are referenced to GND.
3) 1000 , IOOF3' and IOOF4 depend on the cycle time.
4) 1000 depends on the output loading. Specified values are obtained with the outputs open.
5) An initial pause of 1OO~ with high CE is required after power-up before proper device operation is achieved.
6) AC measurements assume tT =5ns.
7) Measured with a load equivalent to 1 TIL load and 100pF.
8) tCHZ, toHz, tWHzdefine the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
9) For write cycles, the input data is latched at the earlier of R/W or CE rising edge. Therefore, the input data must be valid
during the setup time (tosw or tosd and hold time (tOHW or tOHd.
10) All address inputs are latched at the falling edge of CE. Therefore, all the address inputs must be valid during ~sc and tAHc,
11) The two refresh operations, auto refresh and self refresh, are defined by the RFSH pulse width under the condition CE = VH
Auto refresh : RFSH pulse width ~ tFAP (max.)
Self refresh : RFSH pulse width;::: tFAS (min.)
The timing parameter tFRs must be met for proper device operation under the following conditions:
• after self refresh
• if OEiRFSH = "L" after power-up
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
0·209
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