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PDF TC518512PL-80LT Datasheet ( Hoja de datos )

Número de pieza TC518512PL-80LT
Descripción SILICON GATE CMOS PSEUDO STATIC RAM
Fabricantes Toshiba 
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TC518512PL-80LT Hoja de datos, Descripción, Manual
rOSHIBA
TC518512PL/FL/FIL/TRL-70(Ln/80(Ln /10(Ln
SILICON GATE CMOS
524,288 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC518512PL is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits. The TC518512PL utilizes
a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, .b!gh speed and low power storage. The
TC518512PL operates from a single 5V power supply. Refreshing is supported by a refresh (OEIRFSH) input which enables two
types of refreshing - auto refresh and self refresh. The TC518512PL features a static RAM-like interface with a write cycle in which
the input data is written into the memory cell at the rising edge of RNV thus simplifying the microprocessor interface. The
TC518512PL-(LT) is guaranteed over an operating temperature range of -20 - 7LfC.
The TC518512PL is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastiC flat package, and a thin small outline
package (forward type, reverse type).
Features
• Organization: 524,288 words x 8 bits
• Single 5V power supply
• Fast access time
TC518512PL-(LT) Family
crtCEA Access Time
toEA N Access Time
tRC Cycle Time
Power DisSipation
Self Refresh Current
-70
70ns
30ns
115ns
385mW
-80
80ns
30ns
130ns
330mW
2201lA
-10
100ns
40ns
160ns
275mW
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Inputs and outputs TIL compatible
• Wide operating temperature: -20 - 70DC
• Refresh: 2048 refresh cycles/32ms
• Package
- TC518512PL: DIP32-P-600
- TC518512FL: SOP32-P-525
- TC518512FTL: TSOP32-P-400
- TC518512TRL: TSOP32-P-400A
Pin Names
AO - A18 Address Inputs
RIW
Read/Write Control Input
N/R"F'SR
cr
Output Enable Input
Refresh Input
Chip Enable Input
1/01 - 1/08 Data Inputs/Outputs
Voo
GND
Power
Ground
Pin Connection (Top View)
Al8
A16'
AI4
Al2
A7
A6
AS
A4
A3
A2
Al
AO
1101
1/02
1103
GNO
Voo
AIS
AI7
R/VV
Al3
A8
A9
All
mJRRH
Al0
~
1/08
1107
1106
1/05
1104
Al8
A16
AI4
AI2
A7
A6
AS
A4
A3
A2
Al
AO
1101
1102
1103
GNO
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
0-167

1 page

TC518512PL-80LT pdf
Static RAM
TC518512PLlFLlFTLITRL-70(LT)/80(LT)/1 O(LT)
Notes:
1) Stress greater than those listed under "Maximum Ratings" may cause permanent damage to the device.
2) All voltages are referenced to GND.
3) 1000, 100F3' and 100F4 depend on the cycle time.
4) 1000 depends on the output loading. Specified values are obtained with the outputs open.
5) An initial pause of 1OOJlS with high CE is required after power-up before proper device operation is achieved.
6) AC measurements assume tT =5ns.
7) Timing reference levels
Input Levels
Input Reference Levels
Output Reference Levels
V1H =2.6V
V1L =0.6V
V1H =2AV
V1L = 0.8V
VOH =2.2V
VOL =0.8V
INPUT
2.6V
O.6V
OUTPUT
INPUT REFERENCE
LEVEL
2. V
OUTPUT REFERENCE
LEVEL
8) Measured with a load equivalent to 1 TIL load and 100pF.
9) tCHZ' tOHZ, tWHZ define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
10) For write cycles, the input data is latched at the earlier of RIW or CE rising edge. Therefore, the input data must be valid
during the setup time (tosw or tosd and hold time (tOHW or tOHd.
11) All address inputs are latched at the falling edge of CEo Therefore, all the address inputs must be valid during tASC and tAHC.
12) The two refresh operations, auto refresh and self refresh, are defined by the RFSH pulse width under the condition CE =V1H.
Auto refresh : RFSH pulse width ~ tFAP (max.)
Self refresh : RFSH pulse width;;;: tFAS (min.)
The timing parameter tFRS must be met for proper device operation under the following conditions:
• after self refresh
• if OEiRFSH ="L" after power-up
TOSHISA AMERICA ELECTRONIC COMPONENTS. INC.
0-171

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