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PDF GS7166 Data sheet ( Hoja de datos )

Número de pieza GS7166
Descripción 3A Ultra Low Dropout Linear Regulator
Fabricantes GStek 
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3A Ultra Low Dropout Linear Regulator
Features
Maximum 3A Low-Dropout Voltage Regulator
Ultra Low Dropout Voltage
Typically 240mV at 3A Output Current
High Output Accuracy over Line, Load and
Temperature
Build-In Soft-Start
Excellent startup under load from 0 to 3A
Power-On-Reset Monitoring on Both VDD and
VIN Pins
Power-OK Output function
Foldback over Current Protection and
Thermal shutdown
0.1μA (typ) Shutdown Supply Current
Low ESR Output Capacitor(Multi-layer Chip
Capacitors (MLCC)) Applicable
Vout Pull Low Resistance when Disable
PSOP-8TDFN10-3x3
Green Product (RoHS, Lead-Free,
Halogen-Free Compliant)
Applications
Notebook PC Applications
Motherboard Applications
Low Voltage Logic Supplies
Microprocessor and Chipset Supplies
Graphic Cards
Cordless phones
GS7166
General Description
The GS7166 can deliver up to 3A of output
current with a typical dropout voltage of only
240mV using internal n-channel MOSFETs. The
linear regulator uses a separate VDD supply to
power the control circuitry and drive the Internal
n-channel MOSFETs. The output voltage is
adjustable from 0.8V to the voltage that is very
close to VIN.
The GS7166 allows the use of low-ESR ceramic
capacitor as low as 10uF. Moreover the IC
provides good performance on both line transient
response and load transient response.
The GS7166 provides foldback over current limit
and thermal shutdown to prevent the linear
regulator from damage. Built-in soft-start
minimizes stress on the input power source by
reducing capacitive inrush current on start-up.
During start-up, POK remain low until the output
reaches 92% of its rating value.
The GS7166 is available in PSOP-8
TDFN10-3x3 package.
This document is GStek's confidential information. Anyone having confidential obligation to GStek shall keep this document confidential. Any unauthorized
disclosure or use beyond authorized purpose will be considered as violation of confidentiality and criminal and civil liability will be asserted.
Green Solution Technology Co.,LTD.
Rev.:1.2
1
1
JUN-16

1 page




GS7166 pdf
3A Ultra Low Dropout Linear Regulator
GS7166
Recommend Operating Condition (Note 4)
Parameter
Symbol
Supply Voltage
Control Voltage (Note 5)
Junction Temperature
Ambient Temperature
VIN
VDD
TJ
TA
Limits
1.0 < VIN< min{5.2V,VDD}
3.0 < VDD< 5.5
- 40 ~ 125
-40 ~ 85
Units
V
V
°C
°C
Electrical Characteristics
(VIN= VOUT+0.5V, VEN=VDD=5V, CIN=COUT=10uF, TA=TJ=-40~125°C)
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Supply Voltage Section
VDD Operation Voltage
Range
VIN Operation Voltage
Range
Quiescent current
VDD
VIN
IQ
VDD Input current
Control Input Current in
Shutdown
VDD POR Threshold
VDD POR Hysteresis
VIN POR Threshold
VIN POR Hysteresis
IVDD
IVDD_SD
VDDRTH
VINRTH
VDD Input Range, VOUT=VREF
VIN Input Range, VOUT=VREF
VDD=VIN=VEN=5V,IOUT=0A,
VOUT=VREF
VDD=VIN=VEN=5V, IOUT=0A,
VOUT=VREF
VDD=VIN=5.0V, IOUT=0A, VEN=0V
Output Voltage
Reference Voltage
Output Voltage
Accuracy
Line Regulation (VDD)
Line Regulation (VIN)
Load Regulation
(Note 6)
VOUT Pull Low
Resistance
VREF
IOUT=1mA, VOUT=VREF
VLINE_VDD
VLINE_IN
VLOAD
VDD=4V to 5V, IOUT=1mA,
VOUT=VREF, VIN=2V
VIN=1.2V to 5V, IOUT=1mA,
VOUT=VREF
IOUT=1mA to 3 A, VOUT=VREF
VDD=VIN=5.0V, VEN=0V
3.0
1.0
2.4
0.15
0.55
0.13
0.784
-2.0
5.5
min{5.2
V,VDD}
1.0 1.5
1.0 1.5
0.1 12
2.7 3
0.2
0.75 0.95
0.20
0.8 0.816
+2.0
0.03 0.2
0.01 0.1
0.1 1.5
130
V
V
mA
mA
uA
V
V
V
V
V
%
%
%
%
Ω
Green Solution Technology Co.,LTD.
Rev.:1.2
1
5
JUN-16

5 Page





GS7166 arduino
3A Ultra Low Dropout Linear Regulator
GS7166
VOUT
0.8V ~ 1.6V
R1(R2=10KΩ)
0 ~ 10 KΩ
COPTION
470pF~1nF
1.6V ~ 2.4V 10 KΩ ~ 20 KΩ 100pF~500pF
2.4V ~ 3.6V 20 KΩ ~ 30 KΩ 20pF~300pF
Table 2. R2=10KΩ
Figure 4 Feedback Network
Input Capacitor selection
Bypass VIN to ground with a 10uF or greater
capacitor. Bypass VDD to ground with a 1uF
capacitor for normal operation in most appli-
cations. Ceramic, tantalum or aluminum elec-
trolytic capacitors may be selected for input
capacitor. However ceramic capacitors are
recommended due to their significant cost and
space savings. Place the capacitors physically as
close as possible to the device with wide and
direct PCB traces.
Power Dissipation and Layout Considerations
Although internal thermal limiting function is
integrated in GS7166, continuously keeping the
junction near the thermal shutdown temperature
may possibly affect device reliability. For
continuous operation, it is highly recommended to
keep the junction temperature below the
maximum operation junction temperature 125°C
for maximum reliability.
The power dissipation definition in device is:
PD = (VIN − VOUT) x IOUT + VDD x IQ
The maximum power dissipation can be
calculated as:
PD(MAX) = ( TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient
temperature and the θJA is the junction to ambient
thermal resistance.
The thermal resistance θJA for PSOP-8 package
is 75°C/W on the standard JEDEC 51-7 (4 layers,
2S2P) thermal test board. The copper thickness
is 2oz. The maximum power dissipation at TA =
25°C can be calculated by following formula:
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.33W
(SOP-8 Exposed Pad on the minimum layout)
The thermal resistance θJA of PSOP-8 is
determined by the package design and the PCB
design. Copper plane under the exposed pad is
an effective heat sink and is useful for improving
thermal conductivity. As shown in Figure 5, the
amount of copper area to which the PSOP-8 is
mounted affects thermal performance. When
mounted to the standard PSOP-8 pad (Figure
5.a), θJA is 75°C/W. Adding copper area of pad
under the PSOP-8 Figure 5.b) reduces the θJA to
54°C/W. Even further, increasing the copper area
of pad to 70mm2 (Figure 5.c) reduces the θJA to
49°C/W.
Figure 5 (a). Minimum Footprint, JA = 75C/W
Green Solution Technology Co.,LTD.
Rev.:1.2
1
11
JUN-16

11 Page







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