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PDF CD4518BMS Data sheet ( Hoja de datos )

Número de pieza CD4518BMS
Descripción CMOS Dual Up Counters
Fabricantes Intersil Corporation 
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No Preview Available ! CD4518BMS Hoja de datos, Descripción, Manual

CD4518BMS,
CD4520BMS
December 1992
CMOS Dual Up Counters
Features
Pinout
• High Voltage Types (20V Rating)
• CD4518BMS Dual BCD Up Counter
• CD4520BMS Dual Binary Up Counter
• Medium Speed Operation
- 6MHz Typical Clock Frequency at 10V
• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD4518BMS, CD4520BMS
TOP VIEW
CLOCK A 1
ENABLE A 2
Q1A 3
Q2A 4
Q3A 5
Q4A 6
RESET A 7
VSS 8
16 VDD
15 RESET B
14 Q4B
13 Q3B
12 Q2B
11 Q1B
10 ENABLE B
9 CLOCK B
Functional Diagram
Applications
• Multistage Synchronous Counting
• Multistage Ripple Counting
• Frequency Dividers
Description
CD4518BMS Dual BCD Up Counter and CD4520BMS Dual
Binary Up Counter each consist of two identical, internally
synchronous 4-stage counters. The counter stages are
D-type flip-flops having interchangeable CLOCK and
ENABLE lines for incrementing on either the positive-going
or negative-going transition. For single unit operation the
ENABLE input is maintained high and the counter advances
on each positive-going transition of the CLOCK. The
counters are cleared by high levels on their RESET lines.
The counter can be cascaded in the ripple mode by connect-
ing Q4 to the enable input of the subsequent counter while
the CLOCK input of the latter is held low.
CLOCK A
1
ENABLE A
2
RESET A
7
CLOCK B
9
ENABLE B
10
RESET B
15
÷10/÷16
C
R
3
Q1A
4
Q2A
5
Q3A
6
Q4A
÷10/÷16
C
R
11
Q1B
12
Q2B
13
Q3B
14
Q4B
The CD4518BMS and CD4520BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4518B Only
H4S
H1F
*H6P †H6W
†CD4520B Only
VSS = 8
VDD = 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1206
File Number 3342

1 page




CD4518BMS pdf
Specifications CD4518BMS, CD4520BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD ± 1.0µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
Output Current (Source)
IOH5A
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
Note 1
3-6, 11-14
1, 2, 7-10, 15
16
Static Burn-In 2
Note 1
3-6, 11-14
8 1, 2, 7, 9, 10,
15, 16
Dynamic Burn-
In Note 1
-
7, 8, 15
2, 10, 16
3-6, 11-14
1, 9
Irradiation
Note 2
3-6, 11-14
8 1, 2, 7, 9, 10,
15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
7-1210

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