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PDF CD4516BMS Data sheet ( Hoja de datos )

Número de pieza CD4516BMS
Descripción CMOS Presettable Up/Down Counters
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Data Sheet
CD4510BMS, CD4516BMS
December 1992
File Number 3338
CMOS Presettable Up/Down Counters
CD4510BMS Presettable BCD Up/Down Counter and the
CD4516BMS Presettable Binary Up/Down counter consist of
four synchronously clocked D-type flip-flops (with a gating
structure to provide T-type flip-flop capability) connected as
counters. These counters can be cleared by a high level on
the RESET line, and can be preset to any binary number
present on the jam inputs by a high level on the PRESET
ENABLE line. The CD4510BMS will count out of non-BCD
counter states in a maximum of two clock pulses in the up
mode, and a maximum of four clock pulses in the down mode.
If the CARRY IN input is held low, the counter advances up or
down on each positive-going clock transition. Synchronous
cascading is accomplished by connecting all clock inputs in
parallel and connecting the CARRY OUT of a less significant
stage to the CARRY IN of a more significant stage.
The CD4510BMS and CD4516BMS can be cascaded in the
ripple mode by connecting the CARRY OUT to the clock of
the next stage. If the UP/DOWN input changes during a ter-
minal count, the CARRY OUT must be gated with the clock,
and the UP/DOWN input must change while the clock is
high. This method provides a clean clock signal to the sub-
sequent counting stage. (See Figures 13, 14.)
These devices are similar to types MC14510 and MC14516.
The CD4510BMS and CD4516BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4510B Only
*H4W †H45
*FBF †H1F
H6W
†CD4516B Only
Pinout
CD4510BMS, CD4516BMS
TOP VIEW
PRESET ENABLE 1
Q4 2
P4 3
P1 4
CARRY IN 5
Q1 6
CARRY OUT 7
VSS 8
16 VDD
15 CLOCK
14 Q3
13 P3
12 P2
11 Q2
10 UP/DOWN
9 RESET
Features
• High Voltage Types (20V Rating)
• CD4510BMS - BCD Type
• CD4516BMS - Binary Type
• Medium Speed Operation
- fCL = 8MHz Typ. at 10V
• Synchronous Internal Carry Propagation
• Reset and Preset Capability
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Up/Down Difference Counting
• Multistage Synchronous Counting
• Multistage Ripple Counting
• Synchronous Frequency Dividers
Functional Diagram
PRESET ENABLE
4
P1
12
P2
13
P3
3
P4
1
6
Q1
11
Q2
14
Q3
2
Q4
CLOCK
UP/DOWN
CARRY IN
15
10
5
RESET
7
CARRY OUT
9 VDD = 16
VSS = 8
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

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CD4516BMS pdf
CD4510BMS, CD4516BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
VTN VDD = 10V, ISS = -10µA
VTP
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
MAX
25
-0.2
±1
1, 4
+25oC
0.2 2.8
1, 4
+25oC
- ±1
1
1, 2, 3, 4
+25oC
+25oC
3. See Table 2 for +25oC limit.
4. Read and Record
VOH > VOL <
VDD/2 VDD/2
- 1.35 x
+25oC
Limit
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD ± 1.0µA
Output Current (Sink)
Output Current (Source)
IOL5
IOH5A
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
5

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CD4516BMS arduino
CD4510BMS, CD4516BMS
UP/DOWN
PRESET
ENABLE
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
PARALLEL CLOCKING
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
*
CLOCK
RESET
* CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS
IC’S. These negative going glitches do not affect proper CD4029BMS operation. However, if the CARRY OUT signals are used to trigger other edge-
sensitive logic devices, such as FF’S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as
CD4071BMS.
UP/DOWN
PRESET
ENABLE
RIPPLE CLOCKING
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
CLOCK
1/4 CD4071B
RESET
Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the
clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the OR gates
are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded.
FIGURE 15. CASCADING COUNTER PACKAGES
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
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100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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FAX: (886) 2 2715 3029
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