PDF CD4504BMS Data sheet ( Hoja de datos )

Número de pieza	CD4504BMS
Descripción	CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation
Fabricantes	Intersil Corporation
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No Preview Available ! CD4504BMS December 1992 CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation Features Pinout • High Voltage Type (20V Rating) • Independence of Power Supply Sequence Consider- ations - VCC can Exceed VDD - Input Signals can Exceed Both VCC and VDD • Up and Down Level Shifting Capability • Shiftable Input Threshold for Either CMOS or TTL Compatibility • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics CD4504BMS TOP VIEW VCC 1 AOUT 2 AIN 3 BOUT 4 BIN 5 COUT 6 CIN 7 VSS 8 16 VDD 15 FOUT 14 FIN 13 SELECT 12 EOUT 11 EIN 10 DOUT 9 DIN • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Speciﬁcations for Description of ‘B’ Series CMOS Devices” Functional Diagram Description CD4504BMS hex voltage level shifter consists of six circuits which shift input signals from the VCC logic level to the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCC HIGH logic state. When the SELECT input is at a LOW logic state, each circuit translates signals from one CMOS level to another. The CD4504BMS is supplied in these 16-lead outline packages: Frit Seal DIP H1F Ceramic Flatpack H6W VCC * IN (3, 5, 7, 9, 11, 14) VDD LEVEL SHIFTER OUT (2, 4, 6, 10, 12, 15) SELECT * 13 TTL/CMOS MODE SELECT VCC = PIN 1 VDD = PIN 16 VSS = PIN 8 VDD * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Copyright © Intersil Corporation 1999 7-1140 File Number 3336 1 page Speciﬁcations CD4504BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay CMOS - CMOS, VDD > VCC Propagation Delay CMOS - CMOS VCC > VDD Transition Time Input Capacitance SYMBOL CONDITIONS TPLH2 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPLH3 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TTHL TTLH CIN VDD = 10V VDD = 15V Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN - - - - - - - MAX 240 140 UNITS ns ns 400 ns 120 ns 100 ns 80 ns 7.5 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. NOTES 1, 4 1, 4 1, 4 TEMPERATURE +25oC +25oC +25oC MIN - -2.8 - 1, 4 +25oC 0.2 1, 4 +25oC - 1 1, 2, 3, 4 +25oC +25oC VOH > VDD/2 - 3. See Table 2 for +25oC limit. 4. Read and Record MAX 7.5 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading Output Current (Source) IOH5A ± 20% x Pre-Test Reading CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9 100% 5004 1, 7, 9 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A 7-1144 5 Page

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