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PDF KSZ8895FQX Data sheet ( Hoja de datos )
| Número de pieza | KSZ8895FQX | |
| Descripción | Integrated 5-Port 10/100 Managed Ethernet Switch | |
| Fabricantes | Microchip | |
| Logotipo |  |
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KSZ8895MQX/RQX/FQX/MLX
Integrated 5-Port 10/100 Managed Ethernet
Switch with MII/RMII Interface
Features
Advanced Switch Features
• IEEE 802.1q VLAN Support for up to 128 Active
VLAN Groups (Full-Range 4096 of VLAN IDs)
• Static MAC Table Supports up to 32 Entries
• VLAN ID Tag/Untagged Options, Per Port Basis
• IEEE 802.1p/q Tag Insertion or Removal on a Per
Port Basis Based on Ingress Port (Egress)
• Programmable Rate Limiting at the Ingress and
Egress on a Per Port Basis
• Jitter-Free Per Packet Based Rate Limiting Sup-
port
• Broadcast Storm Protection with Percentage Con-
trol (Global and Per Port Basis)
• IEEE 802.1d Rapid Spanning Tree Protocol RSTP
Support
• Tail Tag Mode (1 Byte Added Before FCS) Sup-
port at Port 5 to Inform the Processor Which
Ingress Port Receives the Packet
• 1.4 Gbps High-Performance Memory Bandwidth
and Shared Memory Based Switch Fabric with
Fully Non-Blocking Configuration
• Dual MII with MAC 5 and PHY 5 on Port 5, SW5-
MII/RMII for MAC 5 and P5-MII/RMII for PHY 5
• Enable/Disable Option for Huge Frame Size up to
2000 Bytes Per Frame
• IGMP v1/v2 Snooping (IPv4) Support for Multicast
Packet Filtering
• IPv4/IPv6 QoS Support
• Support Unknown Unicast/Multicast Address and
Unknown VID Packet Filtering
• Self-Address Filtering
Comprehensive Configuration Register Access
• Serial Management Interface (MDC/MDIO) to All
PHYs Registers and SMI Interface (MDC/MDIO)
to All Registers
• High-Speed SPI (up to 25 MHz) and I2C Master
Interface to all Internal Registers
• I/O Pins Strapping and EEPROM to Program
Selective Registers in Unmanaged Switch Mode
• Control Registers Configurable on the Fly (Port-
Priority, 802.1p/d/q, AN…)
QoS/CoS Packet Prioritization Support
• Per Port, 802.1p and DiffServ-Based
• 1/2/4-Queue QoS Prioritization Selection
2016 Microchip Technology Inc.
• Programmable Weighted Fair Queuing for Ratio
Control
• Re-Mapping of 802.1p Priority Field Per Port
Basis
Integrated 5-Port 10/100 Ethernet Switch
• New Generation Switch with Five MACs and Five
PHYs that are Fully Compliant with the IEEE
802.3u Standard
• PHYs Designed with Patented Enhanced Mixed-
Signal Technology
• Non-Blocking Switch Fabric Ensures Fast Packet
Delivery by Utilizing a 1K MAC Address Lookup
Table and a Store-and-Forward Architecture
• On-Chip 64Kbyte Memory for Frame Buffering
(Not Shared with 1K Unicast Address Table)
• Full-Duplex IEEE 802.3x Flow Control (PAUSE)
with Force Mode Option
• Half-Duplex Back Pressure Flow Control
• HP Auto MDI/MDI-X and IEEE Auto Crossover
Support
• SW-MII Interface Supports Both MAC Mode and
PHY Mode
• 7-Wire Serial Network Interface (SNI) Support for
Legacy MAC
• Per Port LED Indicators for Link, Activity, and 10/
100 Speed
• Register Port Status Support for Link, Activity,
Full-/Half-Duplex and 10/100 Speed
• LinkMD® Cable Diagnostic Capabilities
• On-Chip Terminations and Internal Biasing Tech-
nology for Cost Down and Lowest Power Con-
sumption
Switch Monitoring Features
• Port Mirroring/Monitoring/Sniffing: Ingress and/or
Egress Traffic to Any Port or MII
• MIB Counters for Fully Compliant Statistics Gath-
ering; 34 MIB Counters Per Port
• Loopback Support for MAC, PHY, and Remote
Diagnostic of Failure
• Interrupt for the Link Change on Any Ports
Low-Power Dissipation
• Full-Chip Hardware Power-Down
• Full-Chip Software Power-Down and Per Port
Software Power-Down
• Energy-Detect Mode Support <100 mW Full-Chip
Power Consumption When All Ports Have No
DS00002246A-page 1
1 page  
KSZ8895MQX/RQX/FQX/MLX
1.0 INTRODUCTION
1.1 General Description
The KSZ8895MQX/RQX/FQX/MLX is a highly-integrated, Layer 2 managed, five-port switch with numerous features
designed to reduce system cost. Intended for cost-sensitive 10/100Mbps five-port switch systems with low power con-
sumption, on-chip termination, and internal core power controllers, it supports high-performance memory bandwidth and
shared memory-based switch fabric with non-blocking configuration. Its extensive feature set includes power manage-
ment, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, four-queue QoS prioritization,
management interfaces, and MIB counters. The KSZ8895 family provides multiple CPU data interfaces to effectively
address both current and emerging fast Ethernet applications when Port 5 is configured to separate MAC5 with SW5-
MII/RMII and PHY5 with P5-MII/RMII interfaces.
The KSZ8895 family offers three configurations, providing the flexibility to meet different requirements:
• KSZ8895MQX/MLX: Five 10/100Base-T/TX transceivers, One SW5-MII, and One P5-MII interface
• KSZ8895RQX: Five 10/100Base-T/TX transceivers, One SW5-RMII, and One P5-RMII interface
• KSZ8895FQX: Four 10/100Base-T/TX transceivers on Ports 1, 2, 3, and 5 (port 3 can be set to fiber mode). One
100Base-FX transceiver on Port 4. One SW5-MII and One P5-MII interface
All registers of MACs and PHYs units can be managed by the SPI or the SMI interface. MIIM registers can be accessed
through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode.
KSZ8895MQX/RQX/FQX are available in the 128-pin PQFP package. KSZ8895MLX is available as a 128-pin LQFP
package.
FIGURE 1-1:
FUNCTIONAL DIAGRAM
AUTOMDI/MDIX
AUTOMDI/MDIX
AUTOMDI/MDIX
AUTOMDI/MDIX
AUTOMDI/MDIX
P5-MII/RMII
MDC/MDIO FOR MIIM AND SMI
SW5-MII/RMII OR SNI
CONTROL REG SPI I/F
LED
LED
LED
KSZ8895MQX/RQX/FQX/MLX
10/100
T/TX
PHY1
10/100
MAC1
10/100
T/TX
PHY2
10/100
MAC2
10/100
T/TX/FX
PHY3
10/100
T/TX/FX
PHY4
10/100
MAC3
10/100
MAC4
10/100
T/TX
PHY5
10/100
MAC5
LED I/F
SPI
CONTROL
REGISTERS
LOOK UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFERS
MIB
COUNTERS
EEPROM
INTERFACE
2016 Microchip Technology Inc.
DS00002246A-page 5
5 Page 
KSZ8895MQX/RQX/FQX/MLX
TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED)
Pin
Number
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Pin
Name
SMTXEN
SMTXD3
SMTXD2
SMTXD1
SMTXD0
SMTXER
SMTXC/
SMREFCLK
GNDD
VDDIO
SMRXC
SMRXDV/
SMCRSDV
SMRXD3
SMRXD2
SMRXD1
Type,
Note
2-1
IPD
IPD
IPD
IPD
IPD
IPD
I/O
GND
P
I/O
IPD/O
IPD/O
IPD/O
IPD/O
Port
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin Function, Note 2-2
Port 5 Switch MII/RMII transmit enable.
MQX/FQX/MLX: Port 5 Switch MII transmit bit 3.
RQX: no connection for RMII.
MQX/FQX/MLX: Port 5 Switch MII transmit bit 2.
RQX: no connection for RMII.
Port 5 Switch MII/RMII transmit bit 1.
Port 5 Switch MII/RMII transmit bit 0.
MQX/FQX/MLX: Port 5 Switch MII transmit error
RQX: Port 5 Switch RMII transmit error
MQX/FQX/MLX: Port 5 Switch MII transmit clock,
Input: SW5-MII MAC mode, Output: SW5-MII PHY modes.
RQX: Input SW5-RMII 50MHz ±50 ppm reference clock. The
50 MHz clock comes from SMRXC Pin 78 when the device is the
clock mode which the device’s clock comes from 25 MHz crystal/
oscillator from Pins X1/X2. Or the 50 MHz clock comes from exter-
nal 50 MHz clock source when the device is the normal mode which
the device’s clock source comes from SMTXC pin not from X1/X2
pins.
Digital ground.
3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
MQX/FQX/MLX: Port 5 Switch MII receive clock,
Input: SW5-MII MAC mode, Output: SW5-MII PHY mode.
RQX: Output SW5-RMII 50 MHz clock, this clock is used when
opposite doesn’t provide RMII reference clock or the system
doesn’t provide an external 50 MHz clock for the RMII interface.
MQX/FQX/MLX: SMRXDV is for Switch MAC5 MII receive data
valid.
RQX: SMCRSDV is for MAC5 RMII Carrier Sense/Receive Data
Valid Output.
MQX/FQX/MLX: Port 5 Switch MII receive bit 3.
RQX: no connection for RMII
Strap option:
PD (default) = Disable Switch SW5-MII/RMII full-duplex flow control
PU = Enable Switch SW5-MII/RMII full-duplex flow control.
MQX/FQX/MLX: Port 5 Switch MII receive bit 2.
RQX: no connection for RMII
Strap option:
PD (default) = Switch SW5-MII/RMII in full-duplex mode;
PU = Switch SW5-MII/RMII in half-duplex mode.
MQX/FQX/MLX: Port 5 Switch MII receive bit 1.
RQX: Port 5 Switch RMII receive bit 1.
Strap option:
PD (default) = Port 5 Switch SW5-MII/RMII in 100 Mbps mode.
PU = Switch SW5-MII/RMII in 10 Mbps mode.
2016 Microchip Technology Inc.
DS00002246A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8895FQX.PDF ] | |
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