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PDF KSZ8864RMNUB Data sheet ( Hoja de datos )
| Número de pieza | KSZ8864RMNUB | |
| Descripción | Integrated 4-Port 10/100 Managed Switch | |
| Fabricantes | Microchip | |
| Logotipo |  |
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KSZ8864CNX/RMNUB
Integrated 4-Port 10/100 Managed Switch with
Two MACs MII or RMII Interfaces
Features
Advanced Switch Features
• IEEE 802.1q VLAN Support for up to 128 VLAN
Groups (Full-Range 4096 of VLAN IDs)
• Static MAC Table Supports up to 32 Entries
• VLAN ID Tag/Untagged Options, Per Port Basis
• IEEE 802.1p/q Tag Insertion or Removal on a Per
Port Basis Based on Ingress Port (Egress)
• Programmable Rate Limiting at the Ingress and
Egress on a Per Port Basis
• Jitter-Free Per Packet Based Rate Limiting Sup-
port
• Broadcast Storm Protection with Percentage Con-
trol (Global and Per Port Basis)
• IEEE 802.1d Rapid Spanning Tree Protocol RSTP
Support
• Tail Tag Mode (1 Byte Added Before FCS) Sup-
port at Port 4 to Inform the Processor Which
Ingress Port Receives the Packet
• 1.4 Gbps High-Performance Memory Bandwidth
and Shared Memory Based Switch Fabric with
Fully Non-Blocking Configuration
• Dual MII/RMII with MAC 3 SW3-MII/RMII and
MAC 4 SW4-MII/RMII Interfaces
• Enable/Disable Option for Huge Frame Size up to
2000 Bytes Per Frame
• IGMP v1/v2 Snooping (IPv4) Support for Multicast
Packet Filtering
• IPv4/IPv6 QoS Support
• Support Unknown Unicast/Multicast Address and
Unknown VID Packet Filtering
• Self-Address Filtering
Comprehensive Configuration Register Access
• Serial Management Interface (MDC/MDIO) to All
PHYs Registers and SMI Interface (MDC/MDIO)
to All Registers
• High-Speed SPI (up to 25 MHz) and I2C Master
Interface to all Internal Registers
• I/O Pins Strapping and EEPROM to Program
Selective Registers in Unmanaged Switch Mode
• Control Registers Configurable on the Fly (Port-
Priority, 802.1p/d/q, AN…)
QoS/CoS Packet Prioritization Support
• Per Port, 802.1p and DiffServ-Based
• 1/2/4-Queue QoS Prioritization Selection
2016 Microchip Technology Inc.
• Programmable Weighted Fair Queuing for Ratio
Control
• Re-Mapping of 802.1p Priority Field Per Port
Basis
Integrated 4-Port 10/100 Ethernet Switch
• New Generation Switch with Four MACs and Four
PHYs that are Fully Compliant with the IEEE
802.3u Standard
• Non-Blocking Switch Fabric Ensures Fast Packet
Delivery by Utilizing a 1K MAC Address Lookup
Table and a Store-and-Forward Architecture
• On-Chip 64Kbyte Memory for Frame Buffering
(Not Shared with 1K Unicast Address Table)
• Full-Duplex IEEE 802.3x Flow Control (PAUSE)
with Force Mode Option
• Half-Duplex Back Pressure Flow Control
• HP Auto MDI/MDI-X and IEEE Auto Crossover
Support
• LinkMD® TDR-Based Cable Diagnostics to Iden-
tify Faulty Copper Cabling
• MII Interface of MAC Supports Both MAC Mode
and PHY Mode
• Per Port LED Indicators for Link, Activity, and 10/
100 Speed
• Register Port Status Support for Link, Activity,
Full-/Half-Duplex and 10/100 Speed
• On-Chip Terminations and Internal Biasing Tech-
nology for Cost Down and Lowest Power Con-
sumption
Switch Monitoring Features
• Port Mirroring/Monitoring/Sniffing: Ingress and/or
Egress Traffic to Any Port or MII/RMII
• MIB Counters for Fully Compliant Statistics Gath-
ering 34 MIB Counters Per Port
• Loopback Support for MAC, PHY, and Remote
Diagnostic of Failure
• Interrupt for the Link Change on Any Ports
Low-Power Dissipation
• Full-Chip Software Power-Down and Per Port
Software Power-Down
• Energy-Detect Mode Support <0.1W Full-Chip
Power Consumption When All Ports Have No
Activity
• Very-Low Full-Chip Power Consumption (~0.3W),
without Extra Power Consumption on Transform-
ers
DS00002229A-page 1
1 page  
KSZ8864CNX/RMNUB
1.0 INTRODUCTION
1.1 General Description
The KSZ8864CNX/RMNUB is a highly-integrated, Layer 2-managed 4-port switch with optimized design, plentiful fea-
tures and smallest package size. It is designed for cost-sensitive 10/100 Mbps 4-port switch systems with on-chip ter-
mination, lowest-power consumption, and small package to save system cost. It has 1.4 Gbps high-performance
memory bandwidth, shared memory-based switch fabric with full non-blocking configuration. It also provides an exten-
sive feature set such as the power management, programmable rate limiting and priority ratio, tag/port-based VLAN,
packet filtering, quality-of-service (QoS), four queue prioritization, management interface, MIB counters. Port 3 and Port
4 support either MII or RMII interfaces with SW3-MII/RMII and SW4-MII/RMII (see Figure 1-1) for KSZ8864CNX/
RMNUB data interface. An industrial temperature-grade version of the KSZ8864CNXIA and a qualified AEC-Q100 Auto-
motive version of the KSZ8864RMNUB are also available (see the Product Information System section).The
KSZ8864CNX/RMNUB provides multiple CPU control/data interfaces to effectively address both current and emerging
fast Ethernet applications.
The KSZ8864CNX/RMNUB consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technol-
ogy, media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine,
and an on-chip frame buffer memory.
The KSZ8864CNX/RMNUB contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX.
All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of the
PHYs can be accessed through the MDC/MDIO interface. EEPROM can set all control registers by I2C controller inter-
face for the unmanaged mode.
KSZ8864CNX/RMNUB is a 0.11 µm technical device and adding Microchip’s LinkMD® feature, KSZ8864CNX/RMNUB
is completely pin-compatible with the KSZ8864RMN device.
FIGURE 1-1:
FUNCTIONAL DIAGRAM
KSZ8864CNX/RMNUB
AUTO MDI/MDIX
AUTO MDI/MDIX
PORT 3 MAC 3
SW3-MII/RMII
PORT 4 MAC 4
SW4-MII/RMII
MDC/MDIO
SMI, MIIM
CONTROL REG SPI
P1LED[1:0]
P2LED[1:0]
10/100
T/TX
PHY1
10/100
T/TX
PHY2
LED I/F
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
SPI
CONTROL
REGISTERS
LOOK UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFERS
MIB
COUNTERS
EEPROM
INTERFACE
2016 Microchip Technology Inc.
DS00002229A-page 5
5 Page 
KSZ8864CNX/RMNUB
TABLE 2-1: SIGNALS - KSZ8864CNX/RMNUB (CONTINUED)
Pin
Number
59
60
61
62
63
64
Note 2-1
Note 2-2
Pin
Name
Type,
Note
2-1
Port
Pin Function, Note 2-2
Serial bus configuration pin.
For this case, if the EEPROM is not present, the Switch will start
itself with the PS [1.0] = 00 default register values.
Pin Configuration
Serial Bus Configuration
PS1 IPD — PS[1.0]=00
I2C Master Mode for EEPROM
PS[1.0]=01
SMI Interface Mode
PS[1.0]=10
SPI Slave Mode for CPU Interface
PS[1.0]=11
Factory Test Mode (BIST)
PS0 IPD — Serial bus configuration pin.
RST_N
IPU — Reset the device. Active low.
VDDC
X1
P — 1.2V digital core VDD.
I
—
25 MHz crystal clock connection or 3.3V oscillator input. Crystal/
oscillator should be ≤ ±50 ppm tolerance.
X2 O — 25 MHz crystal clock connection.
P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
IPD = Input with internal pull-down.
IPU = Input with internal pull-up.
IPU/O = Input with internal pull-up during reset; output pin otherwise.
IPD/O = Input with internal pull-down during reset; output pin otherwise.
PU = strap pin pull-up
PD = strap pin pull-down
2016 Microchip Technology Inc.
DS00002229A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8864RMNUB.PDF ] | |
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