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PDF KSZ8795CLX Data sheet ( Hoja de datos )
| Número de pieza | KSZ8795CLX | |
| Descripción | Integrated 5-Port 10/100-Managed Ethernet Switch | |
| Fabricantes | Microchip | |
| Logotipo |  |
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KSZ8795CLX
Integrated 5-Port 10/100-Managed Ethernet
Switch with Gigabit GMII/RGMII and MII/
RMII Interfaces
-
Target Applications
• Industrial Ethernet Applications that Employ IEEE
802.3-Compliant MACs. (Ethernet/IP, Profinet,
MODBUS TCP, etc.)
• VoIP Phone
• Set-Top/Game Box
• Automotive
• Industrial Control
• IPTV POF
• SOHO Residential Gateway with Full-Wire Speed
of Four LAN Ports
• Broadband Gateway/Firewall/VPN
• Integrated DSL/Cable Modem
• Wireless LAN Access Point + Gateway
• Standalone 10/100 Switch
• Networked Measurement and Control Systems
Features
• Management Capabilities
- The KSZ8795CLX Includes All the Functions
of a 10/100BASE-T/TX Switch System Which
Combines a Switch Engine, Frame Buffer
Management, Address Look-Up Table,
Queue Management, MIB Counters, Media
Access Controllers (MAC), and PHY Trans-
ceivers
- Non-Blocking Store-and-Forward Switch
Fabric Assures Fast Packet Delivery by Uti-
lizing a 1024-Entries Forwarding Table
- Port Mirroring/Monitoring/Sniffing: Ingress
and/or Egress Traffic to Any Port
- MIB Counters for Fully-Compliant Statistics
Gathering (36 Counters per Port)
- Support Hardware for Port-Based Flush and
Freeze Command in MIB Counter.
- Multiple Loopback of Remote, PHY, and MAC
Modes Support for the Diagnostics
- Rapid Spanning Tree Support (RSTP) for
Topology Management and Ring/Linear
Recovery
• Robust PHY Ports
- Four Integrated IEEE 802.3/802.3u-Compli-
ant Ethernet Transceivers Supporting
10BASE-T and 100BASE-TX
- 802.1az EEE Supported
- On-Chip Termination Resistors and Internal
Biasing for Differential Pairs to Reduce
Power
- HP Auto MDI/MDI-X Crossover Support Elim-
inates the Need to Differentiate Between
Straight or Crossover Cables in Applications
• MAC and GMAC Ports
- Four Internal Media Access Control (MAC1 to
MAC4) Units and One Internal Gigabit Media
Access Control (GMAC5) Unit
- GMII, RGMII, MII or RMII Interfaces Support
for the Port 5 GMAC5 with Uplink
- 2 KByte Jumbo Packet Support
- Tail Tagging Mode (One Byte Added Before
FCS) Support on Port 5 to Inform the Proces-
sor in which the Ingress Port Receives the
Packet and its Priority
- Supports Reduced Media Independent Inter-
face (RMII) with 50 MHz Reference Clock
Output
- Supports Media Independent Interface (MII)
in Either PHY Mode or MAC Mode on Port 5
- LinkMD® Cable Diagnostic Capabilities for
Determining Cable Opens, Shorts, and
Length
• Advanced Switch Capabilities
- Non-Blocking Store-and-Forward Switch
Fabric Assures Fast Packet Delivery by Uti-
lizing 1024 Entry Forwarding Table
- 64 KB Frame Buffer RAM
- IEEE 802.1q VLAN Support for up to 128
Active VLAN Groups (Full-Range 4096 of
VLAN IDs)
- IEEE 802.1p/Q Tag Insertion or Removal on
a Per Port Basis (Egress)
- VLAN ID Tag/Untag Options on Per Port
Basis
- Fully Compliant with IEEE 802.3/802.3u
Standards
- IEEE 802.3x Full-Duplex with Force-Mode
Option and Half-Duplex Back-Pressure Colli-
sion Flow Control
- IEEE 802.1w Rapid Spanning Tree Protocol
Support
2016 Microchip Technology Inc.
DS00002112A-page 1
1 page  
KSZ8795CLX
1.0 INTRODUCTION
1.1 General Description
The KSZ8795CLX is a highly integrated, Layer 2-managed, 5-port switch with numerous features designed to reduce
system cost. It is intended for cost-sensitive applications requiring four 10/100 Mbps copper ports and one 10/100/
1000 Mbps Gigabit uplink port. The KSZ8795CLX incorporates a small package outline, lowest power consumption with
internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, program-
mable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet fil-
tering technology, quality-of-service (QoS) priority with four queues, management interfaces, enhanced MIB counters,
high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The
KSZ8795CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast
Ethernet and Gigabit Ethernet applications where the port 5 GMAC can be configured to any of GMII, RGMII, MII and
RMII modes.
The KSZ8795CLX is built upon industry-leading Ethernet analog and digital technology, with features designed to off-
load host processing and streamline the overall design.
• Four integrated 10/100BASE-T/TX MAC/PHYs
• One integrated 10/100/1000BASE-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces
• Small 80-pin LQFP package
A robust assortment of power-management features including Energy Efficient Ethernet (EEE), PME, and Wake-on-
LAN (WoL) have been designed-in to satisfy energy-efficient environments.
KSZ8795CLX supports two management interface modes of SPI and MIIM only, SPI access all registers, MIIM mode
access all PHYs registers through MDC/MDIO interface.
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
AUTO MDI/MDIX
KSZ8795
10/100
T/TX
EEE PHY1
AUTO MDI/MDIX
10/100
T/TX
EEE PHY2
AUTO MDI/MDIX
10/100
T/TX
EEE PHY3
AUTO MDI/MDIX
10/100
T/TX
EEE PHY4
SW5-GMII/RGMII/MII/RMII
MDC, MDI/O FOR MIIM
CONTROL REG SPI I/F
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100/1000
GMAC 5
SPI
1K LOOK-UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFER
MIB
COUNTERS
LED0 [4:1]
LED1 [4:1]
LED I/F
CONTROL
REGISTERS
2016 Microchip Technology Inc.
DS00002112A-page 5
5 Page 
KSZ8795CLX
TABLE 2-1: SIGNALS - KSZ8795CLX (CONTINUED)
Pin
Number
Pin
Name
Type
Note 2-1
Port
Description
68
SDA_MDIO
Ipu/O
All Data for SPI or MDC/MDIO Interface:
Serial data input in SPI slave mode.
MDC/MDIO interface data input/output.
69 SPIS_N Ipu All SPI Slave Mode Chip Select (Active-Low):
SPI data transfer start in SPI slave mode. When SPIS_N is
high, the KSZ8795CLX is deselected and SPIQ is held in the
high impedance state. A high-to-low transition initiates the SPI
data transfer. This pin is active-low.
70 VDDIO
P — 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
71
GNDD
GND
— Digital Ground.
72 RST_N Ipu — Reset: This active-low signal resets the hardware in the device.
See the timing requirements in this section.
73 VDD12D P — 1.2V Core Power.
74 NC NC — No Connect.
75 ATST NC — No Connect. Factory test pin.
76 VDDAT
P — 3.3V or 2.5V Analog Power.
77 ISET
— Transmit Output Current Set:
This pin configures the physical transmit output current. It
should be connected to GND through a 12.4 kΩ 1% resistor.
78
GNDA
GND
— Analog Ground.
79 XI
I — Crystal Clock Input/Oscillator Input:
When using a 25 MHz crystal, this input is connected to one end
of the crystal circuit. When using a 3.3V oscillator, this is the
input from the oscillator.
The crystal or oscillator should have a tolerance of ±50 ppm.
80
Note 2-1
XO O — Crystal Clock Output:
When using a 25 MHz crystal, this output is connected to one
end of the crystal circuit.
P = power supply; GND = ground; I = input; O = output
I/O = bi-directional
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
OTRI = Output tri-stated.
PU = Strap pin pull-up.
PD = Strap pin pull-down.
NC = No connect or tie-to-ground for this product.
The KSZ8795CLX can function as a managed switch and utilizes strap-in pins to configure the device for different
modes. The strap-in pins are configured by using external pull-up/down resistors to create a high or low state on the
pins which are sampled during the power-down reset or warm reset. The functions are described in following table.
2016 Microchip Technology Inc.
DS00002112A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8795CLX.PDF ] | |
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