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PDF KSZ8061MNX Data sheet ( Hoja de datos )
| Número de pieza | KSZ8061MNX | |
| Descripción | 10BASE-T/100 BASE-TX Physical Layer Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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KSZ8061MNX/MNG
10BASE-T/100 BASE-TX Physical Layer
Transceiver
Highlights
• Single-Chip Ethernet Physical Layer Transceiver
(PHY)
• Quiet-WIRE® technology to reduce line emissions
• Ultra-Deep Sleep standby mode
Target Applications
• Industrial control
• Vehicle on-board diagnostics (OBD)
• Automotive gateways
• Camera and sensor networking
• Infotainment
Features
• Quiet-WIRE programmable EMI filter
• MII interface with MDC/MDIO management inter-
face for register configuration
• On-chip termination resistors for the differential
pairs
• LinkMD®+ receive signal quality indicator
• Fast start-up and link
• Ultra-Deep Sleep standby mode: CPU or signal
detect activated.
• Loopback modes for diagnostics
• Programmable interrupt output
2016 Microchip Technology Inc.
DS00002038A-page 1
1 page  
KSZ8061MNX/MNG
2.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
32-QFN OR WQFN KSZ8061MNX PIN ASSIGNMENT (TOP VIEW)
XI
XO
AVDDH
TXP
TXM
RXP
RXM
AVDDL
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
Bottom paddle is GND
8 17
9 10 11 12 13 14 15 16
LED0/TXER
TXD1
TXD0
TXEN
TXC
RXC
RXD0
RXD1
TABLE 2-1:
Pin
Number
1
2
3
4
5
6
SIGNALS - KSZ8061MNX (32-PIN PACKAGES)
Name
XI
XO
AVDDH
TXP
TXM
RXP
Type
Note 2-1
Description
I Crystal/Oscillator/External Clock Input
25 MHz ±50ppm. This input references the AVDDH power supply.
O Crystal feedback for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
Pwr 3.3V supply for analog TX drivers and XI/XO oscillator circuit.
I/O Physical transmit or receive signal (+ differential)
Transmit when in MDI mode; Receive when in MDI-X mode
I/O Physical transmit or receive signal (‒ differential)
Transmit when in MDI mode; Receive when in MDI-X mode
I/O Physical receive or transmit signal (+ differential)
Receive when in MDI mode; Transmit when in MDI-X mode
2016 Microchip Technology Inc.
DS00002038A-page 5
5 Page 
KSZ8061MNX/MNG
TABLE 2-3: SIGNALS - KSZ8061MNG (48-PIN PACKAGE) (CONTINUED)
Pin Number Pin Name
Type
Note 2-1
Description
39
LED0/
Ipu/O LED0
AUTONEG
Active low. Its function is programmable; by default it indicates link/
activity.
Config Mode: The pull-up/pull-down value is latched as AUTONEG at
the de-assertion of reset. See Table 2-4 for details.
40 LED1/SPEED Ipu/O LED1
Active low. Its function is programmable; by default it indicates link
speed.
Config Mode: The pull-up/pull-down value is latched as SPEED at the
de-assertion of reset. See Table 2-4 for details.
41
VDDIO
Pwr 3.3V, 2.5V, or 1.8V supply for digital I/O.
42
RESET#
Ipu Chip Reset (active low).
43
GND
Gnd Ground.
44
INTRP/
Ipu/O Programmable Interrupt Output (active low (default) or active high)
NAND_Tree#
This pin has a weak pull-up, is open drain like, and requires an external
1.0 kΩ pull-up resistor.
Config Mode: The pull-up/pull-down value is latched as NAND_Tree# at
the de-assertion of reset. See Table 2-4 for details.
45
VDDL
Pwr 1.2V (nominal) supply for digital (and analog).
46
GND
Gnd Ground.
47 REXT I Set PHY transmit output current.
Connect a 6.04 kΩ 1% resistor from this pin to ground.
48
SIGDET
O Signal Detect, active high.
Bottom
Paddle
GND
Gnd Ground.
Note 2-1
Pwr = power supply
Gnd = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value).
Ipd = Input with internal pull-down (see Section 6.0, "Electrical Characteristics" for value).
Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during
power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Section 6.0, "Electrical Characteristics" for value) during
power-up/reset; output pin otherwise.
Ipu/Opu = Input and output with internal pull-up (see Section 6.0, "Electrical Characteristics" for
value).
Note 2-2
MII Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents
valid data to the MAC device.
Note 2-3
MII Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] accepts
valid data from the MAC device.
2016 Microchip Technology Inc.
DS00002038A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8061MNX.PDF ] | |
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