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PDF KSZ8051RNL Data sheet ( Hoja de datos )
| Número de pieza | KSZ8051RNL | |
| Descripción | 10BASE-T/100BASE-TX Automotive Physical Layer Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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KSZ8051MNL/RNL
10BASE-T/100BASE-TX Automotive
Physical Layer Transceiver
Features
• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
• AEC-Q100 Qualified for Automotive Applications
• MII Interface Support (KSZ8051MNL)
• RMII v1.2 Interface Support with a 50 MHz Refer-
ence Clock Output to MAC, and an Option to
Input a 50 MHz Reference Clock (KSZ8051RNL)
• Back-to-Back Mode Support for a 100 Mbps Cop-
per Repeater
• MDC/MDIO Management Interface for PHY Reg-
ister Configuration
• Programmable Interrupt Output
• LED Outputs for Link, Activity, and Speed Status
Indication
• On-Chip Termination Resistors for the Differential
Pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X to Reliably Detect and Cor-
rect Straight-Through and Crossover Cable Con-
nections with Disable and Enable Option
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100 Mbps) and
Duplex (Half/Full)
• Power-Down and Power-Saving Modes
• LinkMD® TDR-Based Cable Diagnostics to Iden-
tify Faulty Copper Cabling
• Parametric NAND Tree Support for Fault Detec-
tion Between Chip I/Os and the Board
• Loopback Modes for Diagnostics
• Single 3.3V Power Supply with VDD I/O Options
for 1.8V, 2.5V, or 3.3V
• Built-In 1.2V Regulator for Core
• Available in 32-pin 5 mm x 5 mm QFN Package
Target Applications
• Automotive In-Vehicle Networking
2016 Microchip Technology Inc.
DS00002310A-page 1
1 page  
KSZ8051MNL/RNL
2.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8051MNL (TOP VIEW)
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
TXP
XO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
Paddle
4
Ground
21
5
(on bottom of chip)
20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
TXD0
TXEN
TXC
INTRP/NAND_Tree#
RXER/ISO
RXC/B-CAST_OFF
RXDV/CONFIG2
VDDIO
TABLE 2-1: SIGNALS - KSZ8051MNL
Pin
Number
Pin
Name
1 GND
2 VDD_1.2
3 VDDA_3.3
4 RXM
5 RXP
6 TXM
Type
Note
2-1
GND
P
P
I/O
I/O
I/O
Description
Ground.
1.2V core VDD (power supplied by KSZ8051MNL)
Decouple with 2.2 µF and 0.1 µF capacitors to ground.
3.3V analog VDD
Physical receive or transmit signal (– differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (– differential)
2016 Microchip Technology Inc.
DS00002310A-page 5
5 Page 
KSZ8051MNL/RNL
TABLE 2-3: SIGNALS - KSZ8051RNL (CONTINUED)
Pin
Number
Pin Name
Type
Note 2-1
Description
Management Interface (MII) Data I/O
11
MDIO
Ipu/Opu This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
12
MDC
Ipu
Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of
13
PHYAD0
Ipu/O reset.
See the Strap-In Options - KSZ8051RNL section for details.
The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of
14
PHYAD1
Ipd/O reset.
See the Strap-In Options - KSZ8051RNL section for details.
RMII mode: RMII Receive Data Output[1] (Note 2-2)
15
RXD1/
PHYAD2
Ipd/O
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
RMII mode: RMII Receive Data Output[0] (Note 2-2)
16
RXD0/
DUPLEX
Ipu/O
Config mode: The pull-up/pull-down value is latched as DUPLEX at the de-
assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD
RMII mode: RMII Carrier Sense/Receive Data Valid output
18
CRS_DV/
CONFIG2
Ipd/O
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the de-
assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
RMII mode: 25 MHz mode: This pin provides the 50 MHz RMII reference clock
output to the MAC. See also XI (pin 9).
19
REF_CLK/
B-CAST_OFF
Ipd/O
50 MHz mode: This pin is a no connect. See also XI (pin 9).
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
RMII mode: RMII Receive Error output
20
RXER/ISO
Ipd/O
Config mode: The pull-up/pull-down value is latched as ISOLATE at the de-
assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
Interrupt output: Programmable interrupt output
This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
21
INTRP/
NAND_Tree#
Ipu/Opu
pull-up resistor.
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset.
See the Strap-In Options - KSZ8051RNL section for details.
22 NC — No connect – This pin is not bonded and can be left floating.
23 TXEN
I RMII Transmit Enable input
24 TXD0
I RMII Transmit Data Input[0] (Note 2-3)
25 TXD1
I RMII Transmit Data Input[1] (Note 2-3)
26 NC NC No connect – This pin is not bonded and can be left floating.
27 NC NC No connect – This pin is not bonded and can be left floating.
The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of
28
CONFIG0
Ipd/O reset.
See the Strap-In Options - KSZ8051RNL section for details.
2016 Microchip Technology Inc.
DS00002310A-page 11
11 Page | ||
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| PDF Descargar | [ Datasheet KSZ8051RNL.PDF ] | |
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