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PDF EDD1232AAFA Data sheet ( Hoja de datos )

Número de pieza EDD1232AAFA
Descripción 128M bits DDR SDRAM
Fabricantes Elpida Memory 
Logotipo Elpida Memory Logotipo



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DATA SHEET
128M bits DDR SDRAM
EDD1232AAFA (4M words × 32 bits)
Description
The EDD1232AAFA is a 128M bits DDR SDRAM
organized as 1,048,576 words × 32 bits × 4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 100-pin plastic LQFP package.
Features
Power supply: VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
Data rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5, 3
Programmable output driver strength: half/weak
Refresh cycles: 4096 refresh cycles/32ms
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
LQFP package with lead free solder (Sn-Bi)
RoHS compliant
Document No. E0432E50 (Ver.5.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005

1 page




EDD1232AAFA pdf
EDD1232AAFA
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
VT
VDD
IOS
PD
TA
Tstg
–1.0 to +3.6
–1.0 to +3.6
50
1.0
0 to +70
–55 to +125
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Parameter
Symbol
min.
typ. max.
Unit Notes
Supply voltage
VDD,
VDDQ
VSS,
VSSQ
2.3
0
2.5 2.7
00
V1
V
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
VDDQ + 0.3
V2
Input low voltage
VIL (DC)
–0.3
VREF – 0.15
V3
Input voltage level,
CK and /CK inputs
VIN (DC)
–0.3
VDDQ + 0.3
V4
Input differential cross point
voltage, CK and /CK inputs
VIX (DC)
0.5 × VDDQ 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V
Input differential voltage,
CK and /CK inputs
VID (DC)
0.36
VDDQ + 0.6
V 5, 6
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Data Sheet E0432E50 (Ver.5.0)
5

5 Page





EDD1232AAFA arduino
Block Diagram
CK
/CK
CKE
A0 to A11, BA0, BA1
/CS
/RAS
/CAS
/WE
EDD1232AAFA
Mode
register
Row
address
buffer
and
refresh
counter
Bank 3
Bank 2
Bank 1
Memory cell array
Bank 0
Column
address
buffer
and
burst
counter
Sense amp.
Column decoder
Data control circuit
Latch circuit
CK, /CK
DLL
Input & Output buffer
DQ
DQS
DM
Data Sheet E0432E50 (Ver.5.0)
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