|
|
PDF EDD10161BBH-TS Data sheet ( Hoja de datos )
| Número de pieza | EDD10161BBH-TS | |
| Descripción | 1G bits DDR Mobile RAM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de EDD10161BBH-TS (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
PRELIMINARY DATA SHEET
1G bits DDR Mobile RAM
WTR (Wide Temperature Range)
EDD10161BBH-TS (64M words × 16 bits)
Specifications
• Density: 1G bits
• Organization: 16M words × 16 bits × 4 banks
• Package: 60-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.7V to 1.95V
• Data rate: 400Mbps/333Mbps (max.)
• 2KB page size
Row address: A0 to A13
Column address: A0 to A9
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge option for each burst
access
• Driver strength: normal, 1/2, 1/4
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8µs
• Operating ambient temperature range
TA = −25°C to +85°C
Features
• DLL is not implemented
• Low power consumption
• Double-data-rate architecture; two data transfers per
one clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver.
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Burst termination by burst stop command and
Precharge command
• Wide temperature range
TA = −25°C to +85°C
• Low Power Function below is not supported
Partal Array Self-Refresh (PASR)
Auto Temperature Compensated Self-Refresh
Deep power-down mode
Document No. E1444E30 (Ver. 3.0)
Date Published October 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008-2009
1 page  
EDD10161BBH-TS
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–0.5 to +2.3
–0.5 to +2.3
50
1.0
–25 to +85
–55 to +125
Unit Note
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = −25°C to +85°C)
Parameter
Pins
Symbol
min.
typ. max.
Unit Notes
Supply voltage
VDD,
VDDQ
VSS,
VSSQ
1.7
0
1.8 1.95
00
V1
V
Input high voltage
All other input VIH
0.8 × VDDQ
—
VDDQ + 0.3
V
Input low voltage
pins VIL
–0.3
—
0.2 × VDDQ
V
DC input voltage level
CK, /CK
VIN (DC)
–0.3
—
VDDQ + 0.3
V
AC Input differential cross
point voltage
VIX
0.4 × VDDQ
0.5 × VDDQ 0.6 × VDDQ V 6
DC input differential voltage
VID (DC)
0.4 × VDDQ
—
VDDQ + 0.6 V 5
AC input differential voltage
VID (AC)
0.6 × VDDQ
—
VDDQ + 0.6 V 5
DC input high voltage
DQ, DM, DQS VIHD (DC) 0.7× VDDQ
—
VDDQ + 0.3
V
DC input low voltage
VILD (DC)
–0.3
—
0.3 × VDDQ
V
AC input high voltage
VIHD (AC) 0.8× VDDQ
—
VDDQ + 0.3
V
AC input low voltage
VILD (AC)
–0.3
—
0.2 × VDDQ
V
Notes: 1. VDDQ must be equal to VDD.
2. VIH (max.) = 2.3V (pulse width ≤ 5ns).
3. VIL (min.) = –0.5V (pulse width ≤ 5ns).
4. All voltage referred to VSS and VSSQ must be same potential.
5. VID (DC) and VID (AC) are the magnitude of the difference between the input level on CK and the input
level on /CK.
6. The value of VIX is expected to be 0.5 × VDDQ and must track variations in the DC level of the same.
Preliminary Data Sheet E1444E30 (Ver. 30)
5
5 Page 
EDD10161BBH-TS
Timing Parameter Measured in Clock Cycle
tCK
Parameter
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write
command delay
(CL = 3)
Burst stop command to DQ high-Z
(CL = 3)
Read command to write command
delay (to output all data)
(CL = 3)
Pre-charge command to high-Z
(CL = 3)
Write command to data in latency
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTZ
tRWD
tHZP
tWCD
Write recovery
tWR
DM to data in latency
Mode register set command cycle
time
Self-refresh exit to non-column
command
Auto-refresh period
tDMD
tMRD
tSREX
tRFC
Power-down entry
tPDEN
Power-down exit to command input tPDEX
CKE minimum pulse width
tCKE
Number of clock cycle
5.0ns
6.0ns
min.
max.
min.
max.
4 + BL/2
4 + BL/2
BL/2
BL/2
3 + BL/2
2 + BL/2
3 3
3 3
3 + BL/2
3 + BL/2
3 3
1 1
3 3
0 0
2 2
24 20
16 13
2 2
1 1
2 2
7.5ns
min.
max.
3 + BL/2
BL/2
2 + BL/2
3
3
3 + BL/2
3
1
2
0
2
16
11
1
1
2
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Preliminary Data Sheet E1444E30 (Ver. 30)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EDD10161BBH-TS.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| EDD10161BBH-TS | 1G bits DDR Mobile RAM | Elpida Memory |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |