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PDF EM48BM1684LBC Data sheet ( Hoja de datos )

Número de pieza EM48BM1684LBC
Descripción 512Mb Mobile Synchronous DRAM
Fabricantes Eorex 
Logotipo Eorex Logotipo



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No Preview Available ! EM48BM1684LBC Hoja de datos, Descripción, Manual

Revision History
Revision 0.1 (Jun. 2012)
- First release.
EM48BM1684LBC
Jun. 2012
www.eorex.com
1/20

1 page




EM48BM1684LBC pdf
Pin Description (Simplified)
EM48BM1684LBC
Pin
F2
G9
F3
H7,H8,J8,J7,J3,
J2,H3,H2,H1,G3,
H9,G2,G1
G7,G8
F8
F7
F9
F1, E8
A8,B9,B8,C9,C8,
D9,D8,E9,E1,D2,
D1,C2,C1,B2,B1,
A2
A9,E7,J9/
A1,E3,J1
A7,B3,C7,D3/
A3,B7,C3,D7
E2
Name
CLK
/CS
CKE
A0~A12
BA0, BA1
/RAS
/CAS
/WE
UDQM, LDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A12) is determined by A0 to A12 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA9) is determined by A0 to A9 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
VDD and VSS are power supply pins for internal circuits.
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
(No Connection)
This pin is recommended to be left No Connection on the
device.
Jun. 2012
www.eorex.com
5/20

5 Page





EM48BM1684LBC arduino
Simplified State Diagram
EM48BM1684LBC
Mode
Register
Set
MRS
Self
Refresh
LF
SE
Ex
LF
SE
IDLE
REF
it
CK
CK
E
E Power
Down
CBR
Refresh
Write
WRITE CKE
Suspend CKE
WRITE
Row
Active
CKE
CKE
adBS Read
wit
Wr hRead
Re
ad R
wit
Write e
h
READ
T
CKE
CKE
Active
Power
Down
READ
Suspend
WRITEA CKE
Suspend CKE
WRITEA
PR
E
PR
E
POWER
ON
Precharge
ite
Precharge
READA
CKE
CKE
READA
Suspend
Manual Input
Automatic Sequence
Jun. 2012
11/20
www.eorex.com

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