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PDF EM488M1644VBB Data sheet ( Hoja de datos )

Número de pieza EM488M1644VBB
Descripción 128Mb Synchronous DRAM
Fabricantes Eorex 
Logotipo Eorex Logotipo



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No Preview Available ! EM488M1644VBB Hoja de datos, Descripción, Manual

eorex
EM488M1644VBB
128Mb (2M×4Bank×16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 2.75V ~ 3.6V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
Ordering Information
Description
The EM488M1644VBB is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 128Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TFBGA-54B(8mmx8mm).
Part No
Organization Max. Freq
EM488M1644VBB-75F
8M X 16
133MHz @CL3
EM488M1644VBB-7F
8M X 16
143MHz @CL3
EM488M1644VBB-75FE
8M X 16
133MHz @CL3
EM488M1644VBB-7FE
8M X 16
143MHz @CL3
EM488M1644VBB-75
8M X 16
133MHz @CL3
EM488M1644VBB-7
8M X 16
143MHz @CL3
Package
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
Grade
Commercial
Commercial
Extend temp
Extend temp
Special request
Special request
Pb
Free
Free
Free
Free
Pb
Pb
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
1/17
www.eorex.com

1 page




EM488M1644VBB pdf
eorex
EM488M1644VBB
Recommended DC Operating Conditions
(VDD=2.75V ~ 3.6V, TA=-10°C ~ 70°C; -25°C ~ +85°C)
Symbol
Parameter
Test Conditions
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
Operating Current (Note 1)
Precharge Standby Current in
Power Down Mode
Precharge Standby Current in
Non-power Down Mode
Active Standby Current in
Power Down Mode
Active Standby Current in
Non-power Down Mode
Operating Current (Burst
Mode) (Note 2)
Refresh Current (Note 3)
Burst length=1,
tRCtRC(min.), IOL=0mA,
One bank active
CKEVIL(max.), tCK=15ns
CKEVIL(max.), tCK=
CKEVIL(min.), tCK=15ns,
/CSVIH(min.)
Input signals are changed
one time during 30ns
CKEVIL(min.), tCK= ,
Input signals are stable
CKEVIL(max.), tCK=15ns
CKEVIL(max.), tCK=
CKEVIL(min.), tCK=15ns,
/CSVIH(min.)
Input signals are changed
one time during 30ns
CKEVIL(min.), tCK= ,
Input signals are stable
tCCD2CLKs, IOL=0mA
tRCtRC(min.)
ICC6 Self Refresh Current
CKE0.2V
*All voltages referenced to VSS.
Note 1: ICC1 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 2: ICC4 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 3: Input signals are changed only one time during tCK (min.)
Note 4: Standard power version.
Max.
70
1
1
20
15
7
5
40
35
100
140
1 (Note 4)
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Recommended DC Operating Conditions (Continued)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
IIL Input Leakage Current
0VIVDDQ, VDDQ=VDD
All other pins not under test=0V
-0.5
IOL Output Leakage Current
0VOVDDQ, DOUT is disabled
-0.5
VOH High Level Output Voltage IO=-2mA
2.4
VOL Low Level Output Voltage IO=+2mA
+0.5
+0.5
0.4
uA
uA
V
V
Jul. 2006
5/17
www.eorex.com

5 Page





EM488M1644VBB arduino
eorex
EM488M1644VBB
Burst Type (A3)
Burst Length
A2 A1 A0
Sequential Addressing
Interleave Addressing
XX0
01
2
XX0
10
01
10
X00
0123
0123
X01
1230
4
X10
2301
1032
2301
X11
3012
3210
000
01234567
01234567
001
12345670
10325476
010
23456701
23016745
011
34567012
8
100
45670123
32107654
45670123
101
56701234
54761032
110
67012345
67452301
111
70123456
76543210
Full Page*
nnn
Cn Cn+1 Cn+2……
-
* Page length is a function of I/O organization and column addressing ×16 (CA0 ~ CA8):
Full page = 512bits
1. Command Truth Table
Command
Symbol
CKE
n-1 n
/CS
/RAS
/CAS
/WE
BA0,
BA1
A10
A11,
A9~A10
Ignore Command
DESL H X H X
X XXX
X
No Operation
NOP H X L H
H HXX
X
Burst Stop
BSTH H X L H H L X X
X
Read
READ H X L H
L HVL
V
Read with Auto Pre-charge READA H X L H
L HVH
V
Write
WRIT H X L H L L V L
V
Write with Auto Pre-charge WRITA H X L L
H HVH
V
Bank Activate
ACT H X L L
H HVV
V
Pre-charge Select Bank
PRE H X L L
H L VL
X
Pre-charge All Banks
PALL H X L L
H L XH
X
Mode Register Set
MRS H X L L
L LLL
V
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
Jul. 2006
11/17
www.eorex.com

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