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PDF EM488M1644VTG Data sheet ( Hoja de datos )
| Número de pieza | EM488M1644VTG | |
| Descripción | 128Mb Synchronous DRAM | |
| Fabricantes | Eorex | |
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eorex
EM488M1644VTG
128Mb (2M4Bank16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 3.3V 0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are sampled at the Rising Edge of the
System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.6us)
Description
The EM488M1644VTG is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 128Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
EM488M1644VTG is available in TSOPII 54Pin
package.
Ordering Information
Part No
EM488M1644VTG-7F
Organization
8M X 16
EM488M1644VTG-6F
8M X 16
EM488M1644VTG-7FE
8M X 16
EM488M1644VTG-6FE
8M X 16
Max. Freq
143MHz @CL3
166MHz @CL3
143MHz @CL3
166MHz @CL3
Package
54pin TSOPll
54pin TSOPll
54pin TSOPll
54pin TSOPll
Grade
Commercial
Commercial
Extended
Extended
Pb
Free
Free
Free
Free
* EOREX reserves the right to change products or specification without notice.
Jan. 2014
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eorex
EM488M1644VTG
Recommended DC Operating Conditions
(VDD, VDDQ=3.3V0.3V, VSS=0V)
Symbol
Parameter
Test Conditions
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3N
ICC4
ICC5
Operating Current (Note 1)
Precharge Standby Current in
Power Down Mode
Precharge Standby Current in
Non-power Down Mode
Active Standby Current in
Power Down Mode
Active Standby Current in
Non-power Down Mode
Operating Current (Burst
Mode) (Note 2)
Auto Refresh Current (Note 3)
Burst length=1,
tRC≥tRC(min.), IOL=0mA,
One bank active
CKE≤VIL(max.), tCK=min
CKE≤VIL(max.), tCK= ∞
CKE≥VIL(min.), tCK=min,
/CS=VIH
CKE≥VIL(min.), tCK= ∞ ,
Input signals are stable
CKE≤VIL(max.), tCK=min
4 banks active
CKE≥VIH(min.), tCK=min,
/CS=VIH(min.)
4 banks active
tCK=min
tCK=min
ICC6 Self Refresh Current
CKE≤0.2V
*All voltages referenced to VSS.
Note 1: ICC1 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 2: ICC4 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min.)
Note 3: Input signals are changed only one time during tCK (min.)
Note 4: Standard power version.
Max.
-6 -7
80 75
10 10
55
30 30
25 25
30 30
Units
mA
mA
mA
mA
mA
mA
45 45 mA
100 90
115 100
5 5(Note 4)
mA
mA
mA
Recommended DC Operating Conditions (Continued)
Symbol
Parameter
IIL Input Leakage Current
IOL Output Leakage Current
VOH High Level Output Voltage
VOL Low Level Output Voltage
Test Conditions
0≤VI≤VDDQ, VDDQ=VDD
All other pins not under test=0V
0≤VO≤VDDQ, DOUT is disabled
IO=-4mA
IO=+4mA
Min. Typ. Max. Units
-10 +10 uA
-10 +10 uA
2.4 V
0.4 V
Jan. 2014
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EM488M1644VTG
Address Input for Mode Register Set
BA1 BA0 A11 A10 A9 A8 A7
Operation Mode
A6 A5 A4 A3 A2 A1 A0
CAS Latency
BT Burst Length
Burst Length
Sequential Interleave A2 A1 A0
1 1 000
2 2 001
4 4 010
8 8 011
Reserved Reserved 1 0 0
Reserved Reserved 1 0 1
Reserved Reserved 1 1 0
Full Page Reserved 1 1 1
Burst Type
Interleave
Sequential
A3
1
0
CAS Latency
A6
A5
A4
Reserved
0
0
0
Reserved
0
0
1
2 010
3 011
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
BA1 BA0 A11 A10 A9 A8 A7
0000000
0000100
Operation Mode
Burst Read with Burst Write
Burst Read with Single Write
Jan. 2014
11/18
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| PDF Descargar | [ Datasheet EM488M1644VTG.PDF ] | |
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