DataSheet.es    


PDF EM47CM1688SBB Data sheet ( Hoja de datos )

Número de pieza EM47CM1688SBB
Descripción 1Gb Double DATA RATE 3 SDRAM
Fabricantes Eorex 
Logotipo Eorex Logotipo



Hay una vista previa y un enlace de descarga de EM47CM1688SBB (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! EM47CM1688SBB Hoja de datos, Descripción, Manual

Revision History
Revision 0.1 (Jun. 2012)
-First release.
EM47CM1688SBB
Jun. 2012
1/38
www.eorex.com

1 page




EM47CM1688SBB pdf
EM47CM1688SBB
Pin Description (Simplified)
Pin
Name
Function
(System Clock)
J7,K7
CK, CK
CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of
CK and negative edge of CK . Output (read) data is referenced to
the crossings of CK and CK (both directions of crossing).
(Chip Select)
All commands are masked when CS is registered HIGH.
L2 CS CS provides for external Rank selection on systems with
multiple Ranks. CS is considered part of the command code.
(Clock Enable)
CKE high activates and CKE low deactivates internal clock
signals and device input buffers and output drivers. Taking CKE
low provides precharge power-down and self- refresh operation
(all banks idle), or active power-down (row active in any bank).
K9
CKE
CKE is asynchronous for self refresh exit. After VREFCA has
become stable during the power on and initialization sequence, it
must be maintained during all operations (including self-refresh).
CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK , ODT and CKE are
disabled during power-down. Input buffers, excluding CKE, are
disabled during self -refresh.
N3,P7,P3,N2,
P8,P2,R8,R2,
T8,R3,L7,R7,
N7
A0~A9,A10/AP,
A11,A12( BC ),
(Address)
Provided the row address (RA0 – RA12) for active commands
and the column address (CA0-CA9) and auto precharge bit for
read/write commands to select one location out of the memory
array in the respective bank. A10 is sampled during a precharge
command to determine whether the precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH). The address inputs
also provide the op-code during Mode Register Set commands.
A12 is sampled during read and write commands to determine if
burst chop (on-the-fly) will be performed. (HIGH: no burst chop,
LOW: burst chopped). See command truth table for details.
M2,N8,M3
BA0, BA1,BA2
(Bank Address)
BA0 – BA2 define to which bank an active, read, write or
precharge command is being applied. Bank address also
determines if the mode register is to be accessed during a MRS
cycle.
(On Die Termination)
ODT (registered HIGH) enables termination resistance internal to
K1
ODT
the DDR3 SDRAM. When enabled, ODT is applied to each DQ,
DQS, DQS , DMU and DML signal. The ODT pin will be ignored if
the Mode Register MR1 is programmed to disable ODT.
Jun. 2012
5/38
www.eorex.com

5 Page





EM47CM1688SBB arduino
EM47CM1688SBB
Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD/2; this is nominally the same.
The transition of single-ended signals through the AC-levels is used to measure setup time. For singleended
components of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but
adds a restriction on the common mode characteristics of these signals.
Single-ended levels for CK, DQS, /CK, /DQS
Symbol Parameter
Min.
Max.
Units Note
VSEH
VSEL
Single-ended high-level for strobes
Single-ended high-level for CK, /CK
Single-ended low-level for strobes
Single-ended low-level for CK, /CK
(VDD/2)+0.175
(VDD/2)+0.175
See Note3
See Note3
See Note3
See Note3
(VDD/2)-0.175
(VDD/2)-0.175
V
V
V
V
1,2
1,2
1,2
1,2
Note1. For CK, /CK use VIH/VIL(AC) of address/command; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.
Note2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on
VREFCA; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level
applies also here.
Note3. These values are not defined, however the single-ended components of differential signals CK, /CK,
DQS, /DQS need to be within the respective limits (VIH(DC) max, VIL(DC) min) for single-ended signals
as well as the limitations for overshoot and undershoot.
Jun. 2012
11/38
www.eorex.com

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet EM47CM1688SBB.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
EM47CM1688SBB1Gb Double DATA RATE 3 SDRAMEorex
Eorex

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar