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PDF GD5F4GQ4R Data sheet ( Hoja de datos )

Número de pieza GD5F4GQ4R
Descripción SPI(x1/x2/x4) NAND Flash
Fabricantes GigaDevice 
Logotipo GigaDevice Logotipo



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No Preview Available ! GD5F4GQ4R Hoja de datos, Descripción, Manual

SPI(x1/x2/x4) NAND Flash
4G
GD5F4GQ4xC
DATASHEET
1

1 page




GD5F4GQ4R pdf
SPI(x1/x2/x4) NAND Flash
2 GENERAL DESCRIPTION
4G
SPI (Serial Peripheral Interface) NAND Flashprovidesan ultra cost-effective while high density non-volatilememory
storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an
attractivealternative toSPI-NOR and standard parallelNAND Flash, with advanced features:
Total pin count is 8, including VCC and GND
Density range from 1Gbit to 4Gbit
Superior write performance and cost per bitover SPI-NOR
Significant low cost than parallelNAND
This low-pin-count NAND Flash memory follows the industry-standard serial peripheralinterface, and always remains the
same pinout from one density toanother. Thecommand setsresemble common SPI-NOR command sets, modified to
handle NANDspecificfunctions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash
memory, with specified designed features to ease host management:
User-selectable internalECC. ECC code is generated internally during a page program operation. When a page
isread to the cache register,the ECC code is detect and correct the errors when necessary. The 128-bytes spare area
is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status.
Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage
collection task, without need of shift in and out of data.
Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power
on, then host can directly read data from cache for easy boot. Also the data is promised correctly by internal ECC.
It is programmed and read in page-based operations, and erased in block-based operations.Data is transferred to or from
the NAND Flash memory array, page by page, to a dataregister and a cache register. The cache register is closest to I/O
control circuits and actsas a data buffer for the I/O data; the data register is closest to the memory array and actsas a data
buffer for the NAND Flash memory array operation.The cache register functions as the buffer memory toenable page and
random data READ/WRITE and copy back operations.These devices also use a SPI statusregister that reports the status
of device operation.
2.1 Product List
Vcc Range
1.7V ~ 2.0V
2.7V ~ 3.6V
Part No.
GD5F4GQ4RCYIG
GD5F4GQ4UCYIG
Page Size
4KByte + 256Byte
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GD5F4GQ4R arduino
SPI(x1/x2/x4) NAND Flash
5.2 HOLD Mode
4G
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated
data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesnt stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low
(if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of
HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK dont care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure3. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5.3 Write Protection
SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock
bits (BP0, BP1, BP2 and INV, CMP) from being overwritten.If the BRWD bit is set to 1 and WP# is LOW, the block protect
bits cannot bealtered.
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