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PDF CD4096BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4096BMS | |
| Descripción | CMOS Gated J-K Master-Slave Flip-Flops | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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December 1992
CD4095BMS
CD4096BMS
CMOS Gated J-K
Master-Slave Flip-Flops
Features
• Set-Reset Capability
• High Voltage Types (20V Rating)
• CD4095BMS Non-Inverting J and K Inputs
• CD4096BMS Inverting and Non-Inverting J and K
Inputs
• 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V
• Gated Inputs
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets all requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Registers
• Counters
• Control Circuits
Description
CD4095BMS and CD4096BMS are J-K Master-Slave Flip-
Flops featuring separate AND gating of multiple J and K
inputs. The gated J-K inputs control transfer of information
into the master section during clocked operation. Information
on the J-K inputs is transferred to the Q and Q outputs on
the positive edge of the clock pulse. SET and RESET inputs
(active high) are provided for asynchronous operation.
The CD4095BMS and CD4096BMS are supplied in these 14
lead outline packages:
Braze Seal DIP
Frit Seal DIP
H4Q
H1A
Pinouts
CD4095BMS
TOP VIEW
NC 1
RESET 2
J1 3
J2 4
J3 5
Q6
VSS 7
14 VDD
13 SET
12 CLOCK
11 K1
10 K2
9 K3
8Q
CD4096BMS
TOP VIEW
NC 1
RESET 2
J1 3
J2 4
J3 5
Q6
VSS 7
14 VDD
13 SET
12 CLOCK
11 K1
10 K2
9 K3
8Q
NC = NO CONNECTION
Functional Diagrams
SET
J1
J2
J3
CLOCK
K1
K2
K3
3
4
5
12
11
10
9
RESET
CD4095BMS
13
J
SQ
8
Q
CL
6
K RQ
Q
2 VDD = 14
VSS = 7
NC = 1
CD4096BMS
SET
J1
J2
J3
CLOCK
K1
K2
K3
3
4
5
12
11
10
9
RESET
13
J
SQ
8
Q
CL
6
K RQ
Q
2 VDD = 14
VSS = 7
NC = 1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1094
File Number 3331
1 page  
Specifications CD4095BMS, CD4096BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
N Threshold Voltage
Delta
∆VTN VDD = 10V, ISS = -10µA
P Threshold Voltage
VTP VSS = 0V, IDD = 10µA
P Threshold Voltage
Delta
∆VTP VSS = 0V, IDD = 10µA
Functional
F VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL VDD = 5V
TPLH
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
TEMPERATURE
+25oC
MIN
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
IDD ± 0.2µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
Output Current (Source)
IOH5A
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
7-1098
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CD4096BMS.PDF ] | |
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