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PDF VSC870 Data sheet ( Hoja de datos )

Número de pieza VSC870
Descripción High Performance Serial Backplane Transceiver
Fabricantes Vitesse Semiconductor 
Logotipo Vitesse Semiconductor Logotipo



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Data Sheet
VSC870
VITESSE
SEMICONDUCTOR CORPORATION
High Performance Serial
Backplane Transceiver
Features
• Performs 32-Bit Parallel to Serial and Serial to
Parallel Functions
• Serial Data Rates are 2.0Gb/s
• Designed in Conjunction with the VSC880 Serial
Crosspoint Switch
• Performs Bit Alignment, Word Alignment and
Cell Alignment
• Three Modes of Operation:
Distributed Control Packet Mode, Central
Control Cell Mode and Direct Mode
• Support for Multicast and Multiple Input Queues
• Supports Priorities, Camp-on and
Retransmission Capability in Packet Mode
• Built-in Flow Control Channel in Packet Mode
• Supports Cell Synchronization in Cell Mode
• Interfaces Directly with Industry Standard
FIFOs
• Contains Redundant Serial I/Os and Internal
Loopback Mode
• 5V Tolerant TTL Inputs
• Single 3.3V Power Supply
• Available in 192 BGA Package
VSC870 Block Diagram
TXIN[31:0]
TXTYP[1:0]
TXEN
RTR
ABORT
BYPASS
WCLK
TXOK
RXOK
RXWA
RXTYP[1:0]
RXOUT[31:0]
ACK/RCLK
RXEN
RFM
RTM/TCLK REN
WSIN WSOUT OOS RESYNEN
Transmit
Control SCRAM
Parallel
to
Serial
Alignment
Word Gen
TXCLK
Generator
Word/Cell
Aligner
RXCLK
Generator
Receive
Control
DeSCRAM
Serial
to
Parallel
CRU
Signal Detect
RESET
SCRAM
TXSA+/TXSA-
CMU
TXSB+/TXSB-
FACLPBK
REFCLK
DLYEN/CCKIN
MODE[1]
MODE[0]
LOOPBACK
RXSA+/RXSA-
RXSB+/RXSB-
RXSEL
TESTEN
VSCTE
CELLSYN
ALIVE
LTIME
G52190-0, Rev 4.1
01/05/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 1

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VSC870 pdf
Data Sheet
VSC870
VITESSE
SEMICONDUCTOR CORPORATION
High Performance Serial
Backplane Transceiver
Symbol
DLYEN/
CCKIN
FACLPBK
WCLK
REFCLK
RESET
TESTEN
LTIME
VSCTE
VDDA
VSSA
Name
I/O
Freq
Type
Description
Delay Enable/Cell Clock
Input
I
<1MHz
TTL
If BYPASS is LOW, this signal can be set HIGH to enable
REN delay mode. In Cell Mode, DLYEN/CCKIN can be
used as an input for cell clock alignment.
Facility Loopback
I
<1MHz
TTL
When this signal is HIGH, the serial input is looped back
to the serial output. It should be normally set LOW.
Word Clock
O
62.5MHz
TTL
The word clock is a delayed version of the WSIN signal.
Local Reference Clock
A 62.5 MHz local reference clock that is used to keep the
I
62.5MHz CRU close to the incoming bit clock frequency before the
TTL alignment process begins. Is also used as a reference
clock for the CMU.
Reset
I
<1MHz
TTL
Global chip reset (active HIGH).
Scan Test Enable
I
<1MHz
TTL
When TESTEN is HIGH, the REFCLK is used in place
of the bit clock for low speed testing. Used for ATE
testing only. Set to logic LOW during normal operation.
Loop Time Mode
I
62.5Mb/s LTIME is set HIGH to use the recovered bit clock for the
TTL transmit side.
NOR Chain Test Enable I
<1MHz
TTL
Used for ATE testing of the parametric NOR chain in the
I/O frame. Set to logic LOW during normal operation.
CMU Power Supply
P
3.3V Clean power supply for CMU
CMU Ground
P 0V Clean ground for CMU
G52190-0, Rev 4.1
01/05/01
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: [email protected]
Internet: www.vitesse.com
Page 5

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VSC870 arduino
Data Sheet
VSC870
VITESSE
SEMICONDUCTOR CORPORATION
High Performance Serial
Backplane Transceiver
1.3 Loopback Mode
The VSC870 supports two loopback functions at the serial interface. If the LOOPBACK signal is set HIGH, the
serial transmit data is looped back to the CRU on the serial receiving side. The transmitted serial data is generated
using the CMU clock. This mode can be used to test the high speed circuitry (except for the serial input/output
buffers) using the low speed parallel interface. The serial data can also be looped back through the I/O of the switch
chip or other connected transceiver if the other device is in FACLPBK mode (see the table below). If FACLPBK is set
HIGH, the receive serial data is recovered using the CRU and looped back to the serial output.
1.4 Redundancy
There are two serial output buffers and two serial input buffers on the transceiver. These can be used to connect
to redundant switch chips or redundant transceivers. The serial inputs are also connected to a signal detector circuit
which is used to determine if there is an average of one transition for every 34 bits of data. If there is, the signal
ALIVE remains HIGH. Which ever input is not connected to the CRU is connected to the signal detector. An example
system would have the redundant serial output connected to a redundant switch chip. This switch chip has the LPBK
bits in the status and control registers set HIGH such that the transceiver output signal (which is looped through the
switch input/output buffer) comes back to itself at the redundant serial input buffer (see Application Note 35). If the
primary switch chip fails, and the ALIVE signal is HIGH on all transceivers, the redundant switch chip can be
activated in its place after it goes through the link initialization process. The signal RXSEL on the transceiver is used
to select the redundant input buffer.
1.5 Operating Modes
The following table summarizes the operating modes for the transceiver that have been discussed in the previous
sections. The pin LTIME selects the source of the bit clock for the transmit side. LTIME is normally set HIGH. In this
case, the received bit clock is use for the transmit bit clock. If LTIME is set LOW, the transceivers CMU is used as the
source of the transmit bit clock. This signal must be set LOW to test the transceiver in loopback mode or when used
as a master transceiver in Direct Mode (see section 4.0).
LOOP
BACK
0
0
0
0
0
0
1
0
0
0
LTIME
1
1
0
1
0
1
0
1
0
X
Control Signal Name
MODE[1]
1
1
0
0
0
1
1
1
1
0
MODE[0]
1
1
1
1
0
1
0
0
0
0
BY
PASS
0
1
1
1
1
1
1
1
1
0
CELL
SYN
0
1
0
0
0
0
0
0
0
1
Description of Operation
Normal Packet Mode operation
Normal Cell Mode operation
Master transceiver in Direct Mode (figure 13)
Slave transceiver in Direct Mode (figure 13)
Master transceiver in Direct Mode (figure 14)
Slave transceiver in Direct Mode (figure 14)
Loopback mode internal to the transceiver
Loopback mode through a VSC880
Loopback mode through an external cable
Mux/Demux Mode - No word alignment
G52190-0, Rev 4.1
01/05/01
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: [email protected]
Internet: www.vitesse.com
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