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PDF VSC8162 Data sheet ( Hoja de datos )

Número de pieza VSC8162
Descripción 2.488 Gbit/sec SONET/SDH 1:16 Demux
Fabricantes Vitesse Semiconductor 
Logotipo Vitesse Semiconductor Logotipo



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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
Features
• 2.488Gb/s 1:16 Demux with Integrated Clock and
Data Recovery
• Recovered Clock and Data Available
• Monolithic Phase Locked Loop
• Digitally Adjustable Serial Data Sampling Point
• Differential Low Speed Outputs
• Differential/Single-ended Reference Clock
• Loss of Lock Detection
• Meets SONET OC-48 and SDH STM-16 Jitter
Tolerance Requirements
General Description
The VSC8162 combines a clock recovery unit (CRU) with a 1:16 demultiplexer on a single chip to directly
generate 16-bit wide data from an incoming 2.488Gb/s NRZ data stream. An on-chip Phase Locked Loop (PLL)
generates a 2.488GHz clock which remains phase locked to the incoming data. The incoming data is retimed
and demultiplexed to a 16-bit word. A Loss of Lock (LOL) signal indicates gross conditions where incoming
data no longer has sufficient transitions to keep the CRU in lock.
VSC8162 Functional Block DIagram
DINVERT
DI+
DI–
REFCK+
REFCK–
PADJ[4:0]
5
Data
Retime
Clock
Recovery
Divide
by 16
RTDO+
RTDO–
D0+
D0–
D15+
D15–
PARITY+
PARITY–
CLK16+
CLK16–
CLKO+
CLKO–
LOL
NOREF
G52209-0, Rev. 2.0
9/14/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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VSC8162 pdf
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
Interface Recommendations
REFCK+, REFCK– Inputs
Internal biasing will position the reference voltage of approximately -1.32V on both the true and comple-
ment inputs. This input can either be DC coupled or AC coupled; it can also be driven single-ended or differen-
tially. Figure 2 shows the configuration for single-ended, AC-coupling operation. In the case of direct coupling
and single-ended input, it is recommended that a stable VREF for ECL levels be used for the complementary
input.
Figure 2: Single-ended AC Coupling for REFCK+, REFCK– Inputs
Chip Boundary
VCC = GND
ZO
CIN REFCK+
-1.32V
-1.32V
RT = ZO
VTT
CSE
REFCK–
VTT VTT = -2V
CIN TYP = 0.1µF
CSE TYP = 0.1µF for single ended applications.
(Capacitor values are selected for REFCLK = 19.44 MHz)
R| | = 1k(Approx.)
G52209-0, Rev. 2.0
9/14/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5

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VSC8162 arduino
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH
1:16 Demux with Clock Recovery
Table 4: PLL Parameters
Parameters
Description
Min Typ Max Units
Conditions
RCd
RCf
fRC
tACQ
tset
tclr
tdensity
tjitter
ttolerance
REFCK Duty Cycle
REFCK Frequency
REFCK Frequency Tolerance
Acquisition time
Loss of Lock set time
Loss of Lock clear time
Maximum zero-timing-content
period
Jitter generationa
Jitter toleranceb
45 — 55
— 19.44 —
-100 — +100
— — 20
2.3 — 100
125 — 250
— 1200 —
— 3.6 4.0
Exceeds mask in Figure 9
%
MHz
ppm
µs
µs
µs
With valid reference clock
From data interruption
From data restoration
UI For 0 BER
ps rms —
a. Measured at the HS clock output for jitter in the 12 kHz to 20 MHz band. Assume 1.2 ps rms input data jitter
b. Error-free operation guaranteed when electrical input signal is subject to jitter specified by mask in Figure 9.
Figure 12: VSC8162 Jitter Mask Specification
sinusoidal
input
jitter
30
15
slope = -20 dB/decade
amplitude
(UI p-p)
3.0
1.5
VSC8162 Mask
SONET/SDH Mask
0.30
0.15
10 600
6k 100k
frequency (Hz)
1000k
G52209-0, Rev. 2.0
9/14/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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