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PDF 894D115I-01 Data sheet ( Hoja de datos )

Número de pieza 894D115I-01
Descripción OC-12/STM-4 and OC-3/STM-1 Clock/Data Recovery Device
Fabricantes IDT 
Logotipo IDT Logotipo



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OC-12/STM-4 and OC-3/STM-1
Clock/Data Recovery Device
894D115I-01
DATA SHEET
General Description
The 894D115I-01 is a clock and data recovery circuit. The device
is designed to extract the clock signal from a NRZ-coded STM-4
(OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The
output signals of the device are the recovered clock and retimed
data signals. Input and output are differential signals for best
signal integrity and to support high clock and data rates. All control
inputs and outputs are single-ended signals. An internal PLL is
used for clock generation and recovery. An external clock input is
provided to establish an initial operating frequency of the clock
recovery PLL and to provide a clock reference in the absence of
serial input data. The device supports a signal detect input and a
lock detect output. A bypass circuit is provided to facilitate factory
tests.
Features
Clock recovery for STM-4 (OC-12/STS-12) and
STM-1 (OC-3/STS-3)
Input: NRZ data (622.08 or 155.52 Mbit/s)
Output: clock signal (622.08MHz or 155.52MHz) and retimed
data signal at 622.08 or 155.52 Mbit/s
Internal PLL for clock generation and clock recovery
Differential inputs can accept LVPECL levels
Differential LVPECL data and clock outputs
Lock reference input and PLL lock output
19.44MHz reference clock input
Full 3.3V supply mode
-40°C to 85°C operating temperature
Available in lead-free (RoHS 6) package
See ICS894D115I for a clock/data recovery circuit with a
TSSOP EPAD package
See ICS894D115I-04 for a clock/data recovery circuit with
LVDS outputs
Block Diagram
CAP
nCAP
DATA_IN Pulldown
nDATA_IN Pullup/Pulldown
REF_CLK Pulldown
STS12 Pulldown
SD Pulldown
LOCK_REFN Pullup
BYPASS Pulldown
PLL
0
1
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
LOCK_DET
Pin Assignment
VCCA
DATA_IN
nDATA_IN
VEE_PLL
LOCK_DET
STS12
REF_CLK
LOCK_REFN
VEE
VCC
1
2
3
4
5
6
7
8
9
10
20 VCCA
19 VEE_PLL
18 CAP
17 nCAP
16 BYPASS
15 SD
14 DATA_OUT
13 nDATA_OUT
12 CLK_OUT
11 nCLK_OUT
894D115I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
894D115I-01 Rev C 2/19/15
1 ©2015 Integrated Device Technology, Inc.

1 page




894D115I-01 pdf
894D115I-01 DATA SHEET
Table 4E. BYPASS Mode Configuration Table
Input
BYPASS Operation
0 Normal operation.
1 PLL bypassed (for factory test). The inverted REF_CLK input signal is output at CLK_OUT/nCLK_OUT.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VCC
Inputs, VI
Outputs, IO
Continuos Current
Surge Current
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
4.6V
-0.5V to VCC + 0.5V
50mA
100mA
81.3C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VCC
VCCA
IEE
ICCA
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
VCC – 0.10
3.3
3.3
Maximum
3.465
VCC
80
10
Units
V
V
mA
mA
Table 5B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VIH Input High Voltage
VIL Input Low Voltage
IIH
Input High Current
REF_CLK,
STS12, BYPASS
VCC = VIN = 3.465V
LOCK_REFN
VCC = VIN = 3.465V
IIL
Input Low Current
REF_CLK,
STS12, BYPASS
VCC = 3.465V, VIN = 0V
LOCK_REFN
VCC = 3.465V, VIN = 0V
2
-0.3
-10
-150
Maximum
VCC + 0.3
0.8
150
10
Units
V
V
µA
µA
µA
µA
OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE
5
Rev C 2/19/15

5 Page





894D115I-01 arduino
894D115I-01 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 894D115I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 894D115I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.20mW
• Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.3V, with all outputs switching) = 277mW + 60mW = 337mW
2. Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
Lower temperature refers to ambient temperature, maximum temperature refers to case temperature.
Table 7. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
81.3°C/W
1
76.9°C/W
2.5
74.8°C/W
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE
11
Rev C 2/19/15

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