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PDF CD4093BC Data sheet ( Hoja de datos )

Número de pieza CD4093BC
Descripción Quad 2-Input NAND Schmitt Trigger
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! CD4093BC Hoja de datos, Descripción, Manual

October 1987
Revised April 2002
CD4093BC
Quad 2-Input NAND Schmitt Trigger
General Description
The CD4093B consists of four Schmitt-trigger circuits.
Each circuit functions as a 2-input NAND gate with Schmitt-
trigger action on both inputs. The gate switches at different
points for positive and negative-going signals. The differ-
ence between the positive (VT+) and the negative voltage
(VT) is defined as hysteresis voltage (VH).
All outputs have equal source and sink currents and con-
form to standard B-series output drive (see Static Electrical
Characteristics).
Features
s Wide supply voltage range: 3.0V to 15V
s Schmitt-trigger on each input
with no external components
s Noise immunity greater than 50%
s Equal source and sink currents
s No limit on input rise and fall time
s Standard B-series output drive
s Hysteresis voltage (any input) TA = 25°C
Typical
VDD = 5.0V VH = 1.5V
VDD = 10V VH = 2.2V
VDD = 15V VH = 2.7V
Guaranteed
VH = 0.1 VDD
Applications
• Wave and pulse shapers
• High-noise-environment systems
• Monostable multivibrators
• Astable multivibrators
• NAND logic
Ordering Code:
Order Number Package Number
Package Description
CD4093BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4093BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Connection Diagram
Top View
© 2002 Fairchild Semiconductor Corporation DS005982
www.fairchildsemi.com

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CD4093BC pdf
Typical Performance Characteristics
Typical Transfer
Characteristics
Guaranteed Trigger Threshold
Voltage vs VDD
Guaranteed Hysteresis vs VDD
Guaranteed Hysteresis vs VDD
Input and Output Characteristics
VNML = VIH(MIN) VOL VIH(MIN) = VT+(MIN)
VNMH = VOH VIL(MAX) VDD VIL(MAX) = VDD VT(MAX)
5
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