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PDF F28F008SA Data sheet ( Hoja de datos )

Número de pieza F28F008SA
Descripción 8-MBIT (1-MBIT x 8) FlashFile MEMORY
Fabricantes Intel 
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28F008SA
8-MBIT (1-MBIT x 8) FlashFileTM MEMORY
Extended Temperature Specifications Included
Y High-Density Symmetrically-Blocked
Architecture
Sixteen 64-Kbyte Blocks
Y Extended Cycling Capability
100 000 Block Erase Cycles
1 6 Million Block Erase
Cycles per Chip
Y Automated Byte Write and Block Erase
Command User Interface
Status Register
Y System Performance Enhancements
RY BY Status Output
Erase Suspend Capability
Y Deep Power-Down Mode
0 20 mA ICC Typical
Y Very High-Performance Read
85 ns Maximum Access Time
Y SRAM-Compatible Write Interface
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Industry Standard Packaging
40-Lead TSOP 44-Lead PSOP
Y ETOX III Nonvolatile Flash Technology
12V Byte Write Block Erase
Intel’s 28F008SA 8-Mbit FlashFileTM Memory is the highest density nonvolatile read write solution for sol-
id-state storage The 28F008SA’s extended cycling symmetrically blocked architecture fast access time
write automation and low power consumption provide a more reliable lower power lighter weight and higher
performance alternative to traditional rotating disk technology The 28F008SA brings new capabilities to porta-
ble computing Application and operating system software stored in resident flash memory arrays provide
instant-on rapid execute-in-place and protection from obsolescence through in-system software updates
Resident software also extends system battery life and increases reliability by reducing disk drive accesses
For high density data acquisition applications the 28F008SA offers a more cost-effective and reliable alterna-
tive to SRAM and battery Traditional high density embedded applications such as telecommunications can
take advantage of the 28F008SA’s nonvolatility blocking and minimal system code requirements for flexible
firmware and modular software designs
The 28F008SA is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages Pin assign-
ments simplify board layout when integrating multiple devices in a flash memory array or subsystem This
device uses an integrated Command User Interface and state machine for simplified block erasure and byte
write The 28F008SA memory map consists of 16 separately erasable 64-Kbyte blocks
Intel’s 28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise
immunity Its 85 ns access time provides superior performance when compared with magnetic storage media
A deep powerdown mode lowers power consumption to 1 mW typical thru VCC crucial in portable computing
handheld instrumentation and other low-power applications The RP power control input also provides
absolute data protection during system powerup down
Manufactured on Intel’s 0 8 micron ETOX process the 28F008SA provides the highest levels of quality
reliability and cost-effectiveness
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290429-005

1 page




F28F008SA pdf
Standard Pinout
28F008SA
Reverse Pinout
290429 – 2
Figure 2 TSOP Lead Configurations
290429 – 3
5

5 Page





F28F008SA arduino
28F008SA
Deep Power-Down
The 28F008SA offers a deep power-down feature
entered when RP is at VIL Current draw thru VCC
is 0 20 mA typical in deep power-down mode with
current draw through VPP typically 0 1 mA During
read modes RP -low deselects the memory
places output drivers in a high-impedence state and
turns off all internal circuits The 28F008SA requires
time tPHQV (see AC Characteristics-Read-Only Op-
erations) after return from powerdown until initial
memory access outputs are valid After this wakeup
interval normal operation is restored The Com-
mand User Interface is reset to Read Array and the
upper 5 bits of the Status Register are cleared to
value 10000 upon return to normal operation
During block erase or byte write modes RP low
will abort either operation Memory contents of the
block being altered are no longer valid as the data
will be partially written or erased Time tPHWL after
RP goes to logic-high (VIH) is required before an-
other command can be written
This use of RP during system reset is important
with automated write erase devices When the sys-
tem comes out of reset it expects to read from the
flash memory Automated flash memories provide
status information when accessed during write
erase modes If a CPU reset occurs with no flash
memory reset proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data Intel’s
Flash Memories allow proper CPU initialization fol-
lowing a system reset through the use of the RP
input In this application RP is controlled by the
same RESET signal that resets the system CPU
Intelligent Identifier Operation
The intelligent identifier operation outputs the manu-
facturer code 89H and the device code A2H for
the 28F008SA The system CPU can then automati-
cally match the device with its proper block erase
and byte write algorithms
The manufacturer- and device-codes are read via
the Command User Interface Following a write of
90H to the Command User Interface a read from
address location 00000H outputs the manufacturer
code (89H) A read from address 00001H outputs
the device code (A2H) It is not necessary to have
high voltage applied to VPP to read the intelligent
identifiers from the Command User Interface
Table 3 Command Definitions
Command
Bus
Cycles Notes
First Bus Cycle
Second Bus Cycle
Req’d
Operation Address Data Operation Address Data
Read Array Reset
1 1 Write
X FFH
Intelligent Identifier
3 2 3 4 Write
X 90H Read
IA IID
Read Status Register
2 3 Write
X 70H Read
X SRD
Clear Status Register
1
Write
X 50H
Erase Setup Erase Confirm
2 2 Write BA 20H Write BA D0H
Erase Suspend Erase Resume
2
Write
X B0H Write
X D0H
Byte Write Setup Write
2 2 3 5 Write
WA 40H Write
WA WD
Alternate Byte Write Setup Write 2 2 3 5 Write
WA 10H Write
WA WD
NOTES
1 Bus operations are defined in Table 2
2 IA e Identifier Address 00H for manufacturer code 01H for device code
BA e Address within the block being erased
WA e Address of memory location to be written
3 SRD e Data read from Status Register See Table 4 for a description of the Status Register bits
WD e Data to be written at location WA Data is latched on the rising edge of WE
IID e Data read from Intelligent Identifiers
4 Following the Intelligent Identifier command two read operations access manufacture and device codes
5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command
6 Commands other than those shown above are reserved by Intel for future device implementations and should not be
used
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