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PDF UM8259A Data sheet ( Hoja de datos )

Número de pieza UM8259A
Descripción Programmable Interrupt Controller
Fabricantes UMC 
Logotipo UMC Logotipo



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<DUMC
UM8259A
Features
• iAPX86, iAPX88 compatible
• MCS-80®, MCS-85® compatible
• Eight-level priority controller
• Expandable to 64 levels
,. Programmable interrupt modes
• Individual request mask capability
• Single +5V supply (no clocks)
• 28-pin dual-in-line package
• Available in EXPRESS
• - Standard temperature range
- Extended temperature range
General Description
The UM8259A Programmable Interrupt Controller handles
up to eight vectored priority interrupts for the CPU, It
is cascadable for up to 64 vectored priority interrupts
without additional circuitry, Packaged in a 28-pin DIP, it
uses NMOS technology and requires a single +5V supply.
Circuitry is static, requiring no clock input.
The UM8259A is designed to minimize the software and
real time overhead in handling multi-level priority
interrupts. It has several modes, permitting optimization
for a variety of system requirements.
The UM8259A is fully compatible with the Intel 8259A.
Software originally written for the 8259A will operate
the UM8259A in all 8259A equivalent modes.
*iAPX86, iAPX88, MCS-80 and MCS-85 are all trademarks of Intel microsystem.
Pin Configuration
Block Diagram
CS
WR
RO
07
D6
D5
D4
D3
D2
D1
DO
CAS 0
CAS 1
GND
VCC
AO
INTA
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IRO
INT
SP/EN
CAS 2
07- 0 0
DATA
BUS
BUFFER
Ri5
WR
AO-
READ!
WRITE
LOGIC
Cs
CAS 0
CAS 1
CAS 2
CONTROL LOGIC
IR1
IIR6
IR7
7-169

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UM8259A pdf
(t)UMC
UMB259A
Pin Description
Symbol
Pin No. Type
Name and Functions
Vee
GND
CS
28
14
1
WR 2
RD 3
D7-DO
4-11
CASo-CAS2 12,13,15
SP/EN
16
INT 17
IRo-IR7 18-25
INTA
Ao
26
27
I Supply: +5V Supply.
I Ground.
I Chip Select: A low on this pin enables RD and WR communication between the
CPU and the UM8259A. INTA functions are independent of CS.
I Write: A low on this pin when CS is low enables the UM8259A to accept command
words from the CPU.
I Read: A low on this pin when CS is low enables the Um8259A to release status
onto the data bus for the CPU.
I/O Bidirectional Data Bus: Control, status and interrupt-vector information is
transferred via this bus.
I/O Cascade Lines: The CAS lines form a private UM8259A bus to control a multiple
UM8259A structure. These pins are outputs for a master UM8259A and inputs for
a slave UM8259A.
I/O Slave Program/Enable Buffer: This is a dual function pin. When in the Buffered
Mode it can be used as an output to control buffer transceivers (EN), When not in
the buffered mode it is used as an input to designate a master (SP = 1) of slave
(SP = 0).
0 Interrupt: This pin goes high whenever a valid interrupt request is asserted. Itis
used to interrupt the CPU, thus it is connected to the CPU's interrupt pin.
I Interrupt Requests: Asynchronous inputs. An intarrupt request is executed by
raising an I R input (low to high), and holding it high until it is acknowledged
(Edge Triggered Model, or just by a high level on an IR input (Level Triggered
Mode).
I Interrupt Acknowledge: This pin is used to enable UM8259A interrupt-vector data
onto the data bus by a sequence of interrupt acknowledge pu Ises issued by the
CPU.
I AO Address Line: This pin acts in conjunction with the CS, WR, and RD pins. It
is used by the UM8259A to decipher various Command Words the CPU writes and
status the CPU wishes to read. It is typically connected to the CPU AO address line
(A 1 for iAPX 86, 88).
Functional Description
Interrupts in Microcomputer Systems
Microcomputer system design requires that I/O devices such
as keyboards, displays, sensors and other components
receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.
The most common method of servicing such devices is the
Polled approach. This is where the processor must test each
device in sequence and in effect "ask" each one if it needs
servicing. It is easy to see that a large portion of the main
program is looping through this continuous polling cycle
and that such a method would have a serious, detrimental
effect on system throughput, thus limiting the tasks that
could be assumed by the microcomputer and reducing the
cost effectiveness of using such devices.
A more desirable method would be one that would allow
the microprocessor to be executing its main program and
only stop to service peripheral devices when it is told
to do so by the device itself. In effect, the method would
provide an external asynchronous input that would inform
the processor that it should complete whatever instruction
that is currently being executed and fetch a new routine
that will service the requesting device. Once this servicing
is complete, however, the processor would resume exactly
where it left off.
Th is method is ca lied Interrupt. It is easy to see that
system throughput would drastically increase, and thus
more task could be assumed by the microcomputer to
further enhance its cost effectiveness.
The Programmable Interrupt Controller (PIC) functions as
an overall manager in an Interrupt-Driven system
environment. It accepts requests from the peripheral
equipment, determines which of the incoming requests
is of the highest importance (priority), ascertains whether
the incoming request has a higher priority value than the
level currently being serviced, and issues an interrupt to
the CPU based on this determination.
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UM8259A arduino
(IlUMC
ICW'
AO D7 D6 DS D4 D3 D2 DJ DO
, ICW4 NEEDED
0= NO ICW4 NEEDED
AO D7 D6 DS D4 D3 D2 D\ DO
, = SINGLE
0= CASCADE MODE
CALL ADDRESS INTERVAL
, = INTERVAL OF 4
0= INTERVAL OF 8
, = LEVEL TRIGGERED MODE
0= EDGE TRIGGERED MODE
A7·AS OF INTERRUPT
VECTOR ADDRESS
(MCS·80/85 MODE ONL V)
ICW3 (MASTER DEVICE)
AO D7 D6 DS D4 D3 D2 D\ DO
AWAS OF INTERRUPT
VECTOR ADDRESS
(MCSBO/85 MODE)
T7-T3 OF INTERRUPT
VECTOR ADDRESS
(S086/8088 MODE)
ICW3 (SLAVE DEVICE)
AO D7 D6 DS D4 D3 D2 D\ DO
I I I1 0 I 0 I 0 I 0 I 0 IID2 IID\ liDO
, = IR INPUT MAS A SLAVE
0= IR INPUT DOES NOT HAVE
A SLAVE
1 , 2 34 5 6 7
0 10 10 1o,
,o 0 1 1 o 0
1
, , ,o 0 o 0 ,
ICW4
, = 8086/8088 MODE
0= MCS·80/S5 MODE
, AUTO EOI
0= NORMAL EO(
§ i f 3 -NON BUFFERED MODE
1 0 -BUFFERED MODE/SLAVE
1 1 -BUFFERED MODE/MASTER
Note,: SLAVE ID IS EQUAL TO THE CORRESPONDING
MASTER IR INPUT.
, = SPECIAL FU LL V NESTED
' - - - - - - - - - - - - t 0 = ~g~~PEC(AL FULLV
NESTED MODE
Figure 5. Initialization Command Word Format
7-179
UM8259A
I

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