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PDF UM82C84A Data sheet ( Hoja de datos )

Número de pieza UM82C84A
Descripción CMOS Clock Generator Driver
Fabricantes UMC 
Logotipo UMC Logotipo



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SUMO
::::====:::CMOS UM82C84A
Clock Generator Driver
Features
• Generates the system clock for CMOS or NMOS
Microprocessors
• Up to 25 MHz operation
• Uses a parallel mode crystal circuit or external frequency
source
• Provides ready synchronization
• Generates system reset output from schm itt trigger
input
• Capable of clock synchronization with other 8284As
• TTL compatible inputs/outputs
• Very low p8wer consumption
• 18 Pi n package
• Single +5V power supply
General Description
The UM82C84A is a high performance CMOS clock
generator-.driver which is designed to service the require-
ments of both CMOS and NMOS microprocessors such as
the 80C86, 80C88, 8086 and the 8088. The chip contains
a crystal controlled oscillator, a divide-by-three counter
and complete "Ready" synchronization and reset logic.
Static CMOS circuit design permits operation with an
external frequency source from DC to 25MHz. Crystal
controlled operation to 25MHz is guaranteed with the
use of a parallel, fundamental mode crystal and two small
load capacitors.
All inputs (except Xl, X2 and RES) are TTL compatible
with a VIH of 2.0 volts over the industrial temperature
and voltage ranges.
Power consumption is a fraction of that of the equivalent
bipolar circuits. This speed-power characteristic of CMOS
permits the designer to custom tailor his system design
with respect to power and/or speed requirements.
Pin Configuration
Block Diagram
CSYNC
PClK
AEN1
RDY1
READY
RDY2
AEN2
ClK
GND
VCC
X1
X2
ASYNC
EFI
Fie
OSC
RES
RESET
Control
Pin
FIC
RES
ROY1
ROY2
AEfIT
AEN2
ASYNC
logical 1
External
Clock
Normal
Bus Ready
Address
Disabled
2 Stage Ready
Synchronization
logical 0
Crystal
Drive
Reset
Bus not
Ready
Address
Enabled
1 Stage Ready
Synchronization
ROY1
ASYNC~--------------------
osc
7-128

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UM82C84A pdf
~1c:::J
~2
X1 ClK
X2
Fie
CSYNC
Figure 5. Clock High and Low Time (Using X1, X2)
UM82C84A
Fie
CSYNC
Figure 6. Clock High and Low Time (Using EFI)
X1
X2
RDY2 OSC
Fie
AEN2
CSYNC
Figure 7. Ready to Clock (Using X1, X2)
Figure 8. Ready to Clock (Using EFI)
2.25V
-IFROM OUTPUT
UNDER TEST
R= 740nFDR All OUTPU;-S EXCEPT ClK
463 n FOR ClK OUTPUT
Cl
Notes:
I(SEE NOTE 3)
1. Cl = 100pF
2. Cl = 30pF
3. Cl INCLUDES PROBE AND JIG CAPACITANCE
Figure 9. Test Load Measurement Conditions
Table 1. Crystal Specifications
Parameter
Frequency
Type of Operation
Unwanted Modes
Load Capacitance
Typical Crystal
2.4-25MHz, Fundamental, "AT" cut
Parallel
-6db (Min)
18-32pf
7-132

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