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PDF UM6551A Data sheet ( Hoja de datos )
| Número de pieza | UM6551A | |
| Descripción | Asynchronous Communication Interface Adapter | |
| Fabricantes | UMC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UM6551A (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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(DUMO
UM6551 / UM6551A
.!,.i.:i;::;t'1~?:t;if~I;);fQ'0~0i~:~::;':':Ji:il~'i:!f!:,:t!:P?:1'i:;i7(ij~~jr~iil{t!~ti!!~tf01;iz;11:;;ji::~;JrJ~Y%;;~i:1~~j,I!~ Asynchronous Communication
Interface Adapter
Features
• On-chip baud rate generator: 15 programmable baud
rates derived from a standard 1.8432 MHz external
crystal (50 to 19,200 baud)
• Programmable interrupt and status register to simplify
software design
• Single +5 volt power supply
• Serial echo mode
• False start b it detect io n
• 8-bit bi-directional data bus for direct communica-
tion with the microprocessor
• External 16x clock input for non-standard baud rates
(up to 125k baud)
• Programmable: word lengths; number of stop bits;
and parity bit generation and detection
• Data set and modem control signals provided
• Parity: (odd, even, none, mark, space)
• Full-duplex or half-duplex operation
• 5,6,7,8, and 9 bit transmission
General Description
The UM6551 is an Asynchronous Communication Adapter
(ACIA) intended to provide for interfacing the 6500/6800
microprocessor families to serial communication data
sets and modems. A unique feature is the inclusion of an
on-chip programmable baud rate generator, with a crystal
being the only external component required.
Pin Configuration
Block Diagram
GND
CSo
CS)
RES
RxC
XTALl
XTAL2
RTS
CTS
TxD
DTR
RxD
RSo
RS)
R/W
1>2
TAO
DB7
DB6
DBs
DB4
DB3
DB2
DB)
DBo
DSR
DCD
VCC
¢2
R/W
~o
CSI
RSo
§
RES
DBo
DB7
CTS
TxD
'iFi'Q
DCD
DSR
RxC
XTALl
XTAL2
RxD
DTR
RTS
7-87
1 page  
UM6551 / UM6551A
XTAL 1
(TRANSMIT
CLOCK INPUT)
tOLY
TxO
Note: TxO rate is 1/16 TxC rate
Figure 4a. Transmit Timing with External Clock
IRQ
(CLEAR)
Figure 4b. Interrupt and Output Timing
1 . . - - - - tcCY --~~
RxC
(INPUT)
Note: RxO rate is 1/16 RxC rate
Figure 4c. Receive External Clock Timing
Transm it/Receive Characteristics
Characteristics
Transmit/Receive Clock Rate
Transmit/Receive Clock High Time
Transmit/Receive Clock low Time
XTAl1 to Tx D Propagation Delay
Propagation Delay (RTS, DTR)
IRO Propagation Delay (Clear)
Symbol
tCCY
tCH
tCl
tDD
tDlY
tiRO
. UM6551
Min.
Max.
400*
-
175 -
175 -
- 500
- 500
- 500
(tr . tt = 10 to 30 ns input clocks only)
* The baud rate with external clocking is: Baud Rate = - - - -
16 x T ccy
UM6551 A
Min.
Max.
400*
-
175 -
175 -
- 500
- 500
- 500
Unit
ns
ns
ns
ns
ns
ns
Interface Signal Description
RES (Reset)
During system initialization a low on the RES input will
cause internal registers to be cleared.
.(p 2 (Input Clock)
The input clock is the system ¢ 2 clock and is used to
trigger all data transfers between the system microprocessor
and the UM6551.
R/W (ReadlWrite)
The RNV is generated by the microprocessor and is used
to control the direction of data transfers. A high on
the RNV pin allows the processor to read the data sup-
plied by the UM6551. A low on the R/W pin allows a
write to the UM655-1-.
IRQ (Interrupt Request)
The I RO pin is an interrupt signal from the interrupt
control logic. It is an open drain output, permitting
several devices to be connected to the common IRO
microprocessor input. Normally a high level, TAO goes
low when an interrupt occurs.
7-91
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet UM6551A.PDF ] | |
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