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PDF UM6522A Data sheet ( Hoja de datos )

Número de pieza UM6522A
Descripción VERSATILE INTERFACE ADAPTER
Fabricantes UMC 
Logotipo UMC Logotipo



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UM6522/ UM6522A
Versatile Interface Adapter(VIA)
Features
• Two 8-bit bidirectional I/O ports
• Two 16-bit programmable timer/counters
• Serial data port
• Single +5V power supply
• TTL compatible expect Port A
• CMOS compatible peripheral Port A lines
• Expanded "handshake" capability allows positive
control of data transfers between processor and periph-
eral devices
• Latched output and input registers
• 1 MHz and 2 MHz operation
General Description
The UM6522 Versatile Interface Adapter (VIA) is a very
flexible I/O control device. In addition, this device con-
tains a pair of very powerful 16-bit interval timers, a serial-
to-parallel/parallel-to-serial shift register and input data
latching on the peripheral ports. Expanded handshaking
capability allows control of bi-directional data transfers
between VIA's in multiple processor systems.
Control of peripheral devices is handled primarily through
two 8-bit bi-directional ports. Each line can be program-
med as either an input or an output. Serveral peripheral
I/O lines can be controlled directly from the interval timers
for generating programmable frequency square waves or
for counting externally generated pulses. To facilitate
control of the many powerful features of this chip, an
interrupt flag register, an interrupt enable register and a
pair of function control registers are provided.
Pin· Configuration
VSS
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
CBl
CB2
VCC
Block Diagram
CAl
CA2
RSO
RSl
RS2
RS3
RES
00
01
02
03
04
05
06
07
<1>2
CSl
CS2
R/Iii
IRQ
DATA
BUS
AS3
1----+-+---- CB1
1 - - - - * - - - _ ce2
PORTB
7':"'63

1 page




UM6522A pdf
(l)UMC
UM6522/ UM6522A
READ IRA
OPERATION
'------------------f/~'-------------------
CA2
"DATA TAKEN"
~---....off
~~CAl
t"DATAR EAD Y" - - - - - - - - - - - - - - - - - - - - - - - - -......----------------...."
ACTIVE
~I-::::TRS2?
--"""-------___
~
TRANSITION
Figure 5b. CA2 Timing for Read Handshake, Handshake Mode
¢2~
WRITE ORA, ORB
-
OPERATION
---./
/
"
~
CA2,CB2
"DATA READY"
~
PA, PB
PERIPHERAL DATA
r " r "i r-J~ i---r I---TWHS
TRS3
.r-
TOS ~
Figure 5c. CA2, CB2 Timing for Write Handshake, Pulse Mode
WRITE ORA, 0: ~"'::::::-/----'\.-"---t TWHS"--, ~
OPE RAT 10 N
' -_______________+_-< ;
CA2,CB2
"DATA READY"
TDS
PA, PB
-+__PERIPHERAL DATA _~~~~~~~~~~~~.~ _______________~~ ~______________
;=>l"CDAAl.TCABTl A KEN" ________________________________________ '
~--TRS4
_ _ _ _ _ _ _ _ _ __
ACTIVE
~
TRANSITION
Figure 5d. CA2, CB2 Timing for Write Handshake, Handshake Mode
PA, PB
PERIPHERAL
~TIL~TPO;r,,------INPUT DATA
---------------1=CAl, CBl
INPUT LATCHING
CONTROL
TAL :::'$=--~-~-~-I~-i-IT-I-O-N----------------
Figure 5e. Peripheral Data Input Latching Timing
7-67

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UM6522A arduino
UM6522/ UM6522A
each time it "times-out". Each of these modes in discussed
separately below.
The T1 counter is depicted in Figure 15 and the latches in
Figure 16.
Reg 4 - Timer 1 Low-Order Counter
~'"-=l:}-COUNT VALUE
WRITE -8 BITS LOADED INTO T1 LOW·ORDER LATCHES. LATCH
CONTENTS ARE TRANSFERRED INTO LOW ORDER COUN·
TER AT THE TIME THE HIGH ORDER COUNTER IS LOADED
(RFG 5),
READ - 8 BITS FROM T1 LOW·ORDER COUNTER TRANSFERRED
TO MPU. IN ADDITION, T1 INTERRUPT FLAG IS RESET (BIT
61N INTERRUPT FLAG REGISTER).
Two bits are provide in the Auxiliary Control Register (bits
6 and 7) to allow selection f the T1 operating modes. The
four possible modes are depicted in Figure 17.
D"'" "Reg 5 - Timer 1 High-Order Counter
E:}-COUNT VALUE
4096
-8192
-----16384
---32768
WRITE -8 BITS LOADED INTO T1 HIGH-ORDER LATCHES. ALSO,
AT THIS TIME BOTH HIGH AND LOW-ORDER LATCHES
TRANSFERRED INTO T1 COUNTER, AND INITIATES
COUNTDOWN. T1 INTERRUPT FLAG ALSO IS RESET.
READ - 8 BITS FROM T1 HIGH-ORDER COUNTER TRANSFERRED
TO MPU
Figure 15. T1 Counter Registers
Reg 6 - Timer 1 Low-Order Latches
-~=~"}-8COUNT VALUE
WRITE -8 BIT LOADED INTO T1 LOW-ORDER LATCHES. THIS
OPERATION IS NO DIFFERENT THAT A WRITE INTO REG 4.
READ - 8 BITS FROM T1 LOW-ORDER LATCHES TRANSFERRED
TO MPU. UNLIKE REG 4 OPERATION. THIS DOES NOT
CAUSE RESET OF T1 INTERRUPT FLAG_
['""I"Reg 7 - Timer 1 High-Order Latches
m:}-COUNT VALUE
4096
8192
16384
32768
WRITE -8 BITS LOADED INTO T1 HIGH-ORDER LATCHES. UNLIKE
REG 4 OPERATION NO LATCH-TO-COUNTER TRANSFERS
TAKE PLACE.
READ - 8 BITS FROM T1 HIGH-ORDERLATCHES TRANSFERRED
TO MPU.
Figure 16. T1 Latch Registers
Reg 11 - Auxiliary Control Register
Tl TIMER CONTROL - - - - - - - - - - '
76
o0
01
10
11
OPERATION
TIMED INTERRUPT EACH TIME T1 IS LOADED
CONTINUOUS INTERRUPTS
TIMED INTERRUPT EACH TIME Tl IS LOADED
CONTINUOUS INTERRUPTS
PB7
DISABLED
ONE-SHOT OUTPUT
SQUARE WAVE OUTPUT
T2TIMERCONTROL----------~
5 OPERATION
o TIMED INTERRUPT
1 COUNT DOWN WITH PULSES ON PB6
4 32
0 o0
o0 1
o1 0
o1 1
10 0
1 o1
110
111
OPERATION
DISABLED
SHIFT IN UNDER CONTROL OF T2
SHIFT IN UNDER CONTROL OF 1/>2
SHIFT IN UNDER CONTROL OF EXT CLK
SHIFT OUT FREE RUNNING AT T2 RATE
SHIFT OUT UNDER CONTROL OF T2
SHIFT OUT UNDER CONTROL OF 1/>2
SHIFT OUT UNDER CONTROL OF EXT CLK
Figure 17. Auxiliary Control Register
Note: The processor does not wr ite directly into the low order cou nter (Tl C - L). Instead, th is half of the counter is loaded automatically from
the low order latch when the processor writes into the high order counter. In fact, it may not be necessary to write to the low order counter in
some applications since the timing operation is triggered by writing to th high order counter.
7-73

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