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PDF UM6521A Data sheet ( Hoja de datos )
| Número de pieza | UM6521A | |
| Descripción | Peripheral Interface Adapter | |
| Fabricantes | UMC | |
| Logotipo |  |
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<DUMC
;========= UM6521 / UM6521A
Peripheral Interface Adapter(PIA)
Features
• Extended performance version of UM6520
• Single +5V power supply
• Two 8-bit bi-directional I/O ports with individual data
direction control
• CMOS-compatible peripheral port A lines
• Automatic "handshake" control of data transfers
• Programmable interrupt capability
• Automatic initialization on power up
• 1 and 2 MHz versions
• Direct replacement for Motorola MC6821
General Descr~ption
The UM6521/A Peripheral Interface Adapter (PIA) is
designed to provide a broad range of peripheral control to
microcomputer systems. It is functionally compatible
with the UM6520, but with more drive capability and
improved performance. Control of peripheral devices
is accomplished through two 8-bit bi-directional I/O ports.
Each 1/0 line may be programmed to be either an input
or an output. In addition, four peripheral control lines
are provided to perform "handshaking" during data
transfers.
Pin Configuration
Block Diagram
vss
PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CB1
CB2
VCC
CA1
CA2
IROA
IROB
RSD
RS1
RES
DO
01
02
03
04
05
06
07
1/>2
CS1
CS2
CSD
R/W
MICRO-
PROCESSORS
UM650X
8-BIT ¢=>
DATA'BUS
.
UM66211
6521A
CONTROL¢=>
CONTROL
8-BIT
DATA PORT
8-BIT
DATA PORT
PERIPHERAL
DEVICES-
PRINTERS,
DISPLAYS, ETC.
CONTROL
7-52
1 page  
UM6521/UM6521A
Interface Signal Description
RES (Resed
This signal is used to initialize the PIA. A low signal on
the RES input causes all internal registers to be ~Ieared.
rp2 (Input Clock)
This input is the system rp2 Clock and is used to trigger'
all data transfers between the microprocessor and the
PIA.
R/W (Read/Write)
This signal is generated by the microprocessor a-nd is used
to control the direction of data transfers. A high on the
R/W signal permits the processor to read data supplied by
the PIA; a low on the R/W signal permits the processor to
Write into the PIA.
IROA, IROB {,Interrupt Requests)
IROA and fR013 are interrupt lines generated by the PIA
for ports A and B respectively. These signa Is are active
low signals and have open-drain outputs, thus allowing
multiple IRO signals from multiple PIA's to be wire-ORed
together before connecting to the processor IRO signal
input.
Do· D7 (Data Bus)
,.These eight data bus lines are used to transfer data informa-
tion between the processor and the PIA. These signals
are bi-directional and are normally highimapedance except
when selected for a read operation.
CSO, CS1, CS2 (Chip Selects)
The PIA is selected when CSO andCS1 are high and CS2
is low. These three chip select lines are normally connected
to the processor address lines either directly or through
external decoder circuits.
RSO, RS1(Register Selects)
These two signals are used to select the various registers
inside the PIA.
Internal Architecture
The UM6520 is organized into two independent sections
referred to as the "A Side" and the "B Side." Bach section
consists of a Control Register (CRA, CRB), Data Direction
Register (DDRA, DDRB), Output Register (ORA, ORB),
Interrupt Status Control and the buffers necessary to drive
the Peripheral Interface buses. Figure 12 is a block diagram
of the UM6521.
-IRQA----------------------------------------------~ INTERRUPTSTATUS
CONTROL A
CAl
CA2
OO __--~r-----_,
0 1 - - - - - -. . . . .
02-------1
03-------1
0 4 _ - - - -.....
0 5 _ - - - -.....
OATA BUS
BUFFERS
(OBB)
0 6 _ - - - -.....
__ __.J07----~1- ~
PERIPHERAL
OUTPUT
REGISTER A
(ORA)
OATAINPUT
REGISTER
(OIR)
PERIPHERAL
OUTPUT
REGISTER B
(ORB)
csa
CSl
CS2
RSO
RSl
RiW
ENABLE
RESET
CHIP
SELECT
ANO
R/W
CONTROL
INPUT BUS
' - - - - - - - - - -..... INTERRUPT STATUS
I R Q B _ - - - - - - - - - - - - - - - - - - - - - -__--------------------~
CONTROL B_
Figure 12. UM6521 Block Diagram
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
PB2
PB3
PB4
PB5
PB6
PB7
CBl
CB2
7-56
5 Page 
UM6521 / UM6521A
CA2/CB2 INPUT MODES
Bit 5
CRA (CRB)
Bit 4 Bit3
000
001
Active Transition
of Input Signal*
Negative
Negative
0 10
0 11
Positive
Positive
IRCA (lROB) Interrupt Outputs
Disable - remains high
Enable - goes low when bit 6 in CRA (CRB) is set by active
transition of signal on CA2 (CB2)
Disable - remains high
Enable - as explained above
*Note: Bit 6 of CRA (CRB) will be set to a logic 1 by an active transition of the CA2 (CB2) signal. This is independent of
the state of. Bit 3 in CRA (CRB).
CA2 OUTPUT MODES
Bit5
CRA
Bit 4
Bit3
100
Mode
"Handshake"
on Read
1 0 1 Pulse Output
1 1 0 Manual Output
1 1 1 Manual Output
Descriptions
CA2 is set high on an active transition of the CA1 interrupt
input signal and set low by a microprocessor "Read A Data"
operation. This allows positive control of data transfers from
the peripheral device to the microprocessor.
CA2 goes low for one cycle after a "Read A Data" operation.
This pulse can be used to ~ignal the peripheral device that data
was taken.
CA2 set low
CA2 set high
CB2 OUTPUT MODES
Bit 5
CRB
Bit 4
Bit 3
10 0
10 1
1 10
111
Mode
Descriptions
"Handshake"
on Write
Pulse Output
Manual Output
Manual Outp'ut
CB2 is set low on microprocessor "Write B Data" operation
and is set high by an active transition of the CBl interrupt
input signal. This allows positive control of data transfers
from the microprocessor to the peripheral device.
CB2 goes low for one cycle after a microprocessor "Write B
Data" operation. This can be used to signal the peripheral
device that data is available.
CB2 set low
CB2 set high
Figure 17. Summary of Operation of Control Lines
Ordering Information
Part Number
UM6521
UM6521A
Speed
1 MHz
2 MHz
Package
Plastic
Plastic
7-62
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet UM6521A.PDF ] | |
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