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Número de pieza | LAN9118 | |
Descripción | High Performance Single-Chip 10/100 NonPCI Ethernet Controller | |
Fabricantes | SMSC Corporation | |
Logotipo | ||
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LAN9118
High Performance
Single-Chip 10/100 Non-
PCI Ethernet Controller
PRODUCT FEATURES
Datasheet
Highlights
■ Optimized for the highest data-rate applications such
as high-definition video and multi-media applications
■ Efficient architecture with low CPU overhead;
■ Easily interfaces to most 32-bit and 16-bit embedded
CPU’s
■ Integrated PHY
■ Supports audio & video streaming over Ethernet:
multiple high-definition (HD) MPEG2 streams
■ Pin compatible with other members of LAN9118
family (LAN9117, LAN9116 and LAN9115)
Target Applications
■ Video distribution systems, multi-room PVR
■ High-end Cable, satellite, and IP set-top boxes
■ Digital video recorders
■ High definition televisions
■ Digital media clients/servers
■ Home gateways
Key Benefits
■ Supports highest performance applications
— Highest performing non-PCI Ethernet controller in the
market
— 32-bit interface with fast bus cycle times
— Burst-mode read support
■ Eliminates dropped packets
— Internal buffer memory can store over 200 packets
— Supports automatic or host-triggered PAUSE and back-
pressure flow control
■ Minimizes CPU overhead
— Supports Slave-DMA
— Interrupt Pin with Programmable Hold-off timer
■ Reduces system cost and increases design flexibility
— SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
— Low-cost, low--pin count non-PCI interface for
embedded designs
■ Reduced Power Modes
— Numerous power management modes
— Wake on LAN*
— Magic packet wakeup*
— Wakeup indicator event signal
— Link Status Change
■ Single chip Ethernet controller
— Fully compliant with IEEE 802.3/802.3u standards
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and Half-duplex support
— Full-duplex flow control
— Backpressure for half-duplex flow control
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
■ Flexible address filtering modes
— One 48-bit perfect address
— 64 hash-filtered multicast addresses
— Pass all multicast
— Promiscuous mode
— Inverse filtering
— Pass all incoming with status report
— Disable reception of broadcast packets
■ Integrated Ethernet PHY
— Auto-negotiation
— Automatic polarity detection and correction
■ High-Performance host bus interface
— Simple, SRAM-like interface
— 32/16-bit data bus
— Large, 16Kbyte FIFO memory that can be allocated to
RX or TX functions
— One configurable host interrupt
■ Miscellaneous features
— Low profile 100-pin TQFP package; green, lead free
package also availaible
— Integral 1.8V regulator
— General Purpose Timer
— Support for optional EEPROM
— Support for 3 status LEDs multiplexed with
Programmable GPIO signals
■ 3.3V Power Supply with 5V tolerant I/O
■ 0 to 70°C
* Third-party brands and names are the property of their respective
owners.
SMSC LAN9118
DATASHEET
Revision 1.1 (05-17-05)
1 page High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.10 RX_DP_CTRL—Receive Datapath Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.11 RX_FIFO_INF—Receive FIFO Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.12 TX_FIFO_INF—Transmit FIFO Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.13 PMT_CTRL— Power Management Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.14 GPIO_CFG—General Purpose IO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.15 GPT_CFG-General Purpose Timer Configuration Register . . . . . . . . . . . . . . . . . . . . . . 83
5.3.16 GPT_CNT-General Purpose Timer Current Count Register . . . . . . . . . . . . . . . . . . . . . . 84
5.3.17 ENDIAN—Endian Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.18 FREE_RUN—Free-Run 25MHz Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.19 RX_DROP– Receiver Dropped Frames Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register . . . . . . . . . . . . . . . . . 86
5.3.21 MAC_CSR_DATA – MAC CSR Synchronizer Data Register . . . . . . . . . . . . . . . . . . . . . 86
5.3.22 AFC_CFG – Automatic Flow Control Configuration Register . . . . . . . . . . . . . . . . . . . . . 87
5.3.23 E2P_CMD – EEPROM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.24 E2P_DATA – EEPROM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.4 MAC Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.4.1 MAC_CR—MAC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.4.2 ADDRH—MAC Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.4.3 ADDRL—MAC Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.4.4 HASHH—Multicast Hash Table High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.4.5 HASHL—Multicast Hash Table Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.4.6 MII_ACC—MII Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.4.7 MII_DATA—MII Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4.8 FLOW—Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4.9 VLAN1—VLAN1 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.4.10 VLAN2—VLAN2 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.4.11 WUFF—Wake-up Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.4.12 WUCSR—Wake-up Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.5 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.5.1 Basic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.5.2 Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.5.3 PHY Identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.5.4 PHY Identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.5.5 Auto-negotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.5.6 Auto-negotiation Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.5.7 Auto-negotiation Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5.8 Mode Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5.9 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.5.10 Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.5.11 Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.5.13 PHY Special Control/Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.1 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.1.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 110
6.1.2 Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2 PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3 PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.4 RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.5 RX Data FIFO Direct PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.6 PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.7 TX Data FIFO Direct PIO Writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.8 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.9 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SMSC LAN9118
5
DATASHEET
Revision 1.1 (05-17-05)
5 Page High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
1.1 Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal
Block Diagram".
+3.3V
25MHz
EEPROM
(Optional)
PME
Wakup Indicator
Power Management
3.3V to 1.8V
Regulator
PLL
EEPROM
Controller
SRAM I/F
IRQ
FIFO_SEL
Host Bus Interface
(HBI)
PIO Controller
Interrupt
Controller
GP Timer
2kB to 14kB
Configurable TX FIFO
TX Status FIFO
RX Status FIFO
2kB to 14kB
Configurable RX FIFO
10/100
Ethernet
MAC
MIL - RX Elastic
Buffer - 128 bytes
MIL - TX Elastic
Buffer - 2K bytes
10/100
Ethernet
PHY
LAN
Figure 1.2 Internal Block Diagram
1.2
10/100 Ethernet PHY
The LAN9118 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in
either full or half duplex configurations. The PHY block includes auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
1.3 10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance
especially in full duplex mode. The data paths connect to the PIO interface Function via separate
busses to increase performance. Payload data as well as transmit and receive status is passed on
these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is
accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media
Independent Interface) port internal to the LAN9118. The MAC CSR's also provides a mechanism for
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly
accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and
the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer
can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working
SMSC LAN9118
11
DATASHEET
Revision 1.1 (05-17-05)
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet LAN9118.PDF ] |
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LAN9116 | Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller | Microchip |
LAN9116 | Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller | SMSC Corporation |
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