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PDF LAN9118 Data sheet ( Hoja de datos )
| Número de pieza | LAN9118 | |
| Descripción | High Performance Single-Chip 10/100 Non-PCI Ethernet Controller | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LAN9118 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LAN9118
High Performance Single-Chip 10/100 Non-PCI
Ethernet Controller
Highlights
• Optimized for the highest data-rate applications
such as high-definition video and multi-media
applications
• Efficient architecture with low CPU overhead
• Easily interfaces to most 32-bit and 16-bit embed-
ded CPU’s
• Integrated PHY
• Supports audio & video streaming over Ethernet:
multiple high-definition (HD) MPEG2 streams
• Pin compatible with other members of LAN9118
family (LAN9117, LAN9116 and LAN9115)
Target Applications
• Video distribution systems, multi-room PVR
• High-end Cable, satellite, and IP set-top boxes
• Digital video recorders
• High definition televisions
• Digital media clients/servers
• Home gateways
Key Benefits
• Supports highest performance applications
- Highest performing non-PCI Ethernet control-
ler in the market
- 32-bit interface with fast bus cycle times
- Burst-mode read support
• Eliminates dropped packets
- Internal buffer memory can store over 200
packets
- Supports automatic or host-triggered PAUSE
and back-pressure flow control
• Minimizes CPU overhead
- Supports Slave-DMA
- Interrupt Pin with Programmable Hold-off
timer
• Reduces system cost and increases design flexi-
bility
- SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
- Low-cost, low--pin count non-PCI interface
for embedded designs
• Reduced Power Modes
- Numerous power management modes
- Wake on LAN*
- Magic packet wakeup*
- Wakeup indicator event signal
- Link Status Change
• Single chip Ethernet controller
- Fully compliant with IEEE 802.3/802.3u stan-
dards
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and check-
ing
- Automatic payload padding and pad removal
- Loop-back modes
• Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets
• Integrated Ethernet PHY
- Auto-negotiation
- Automatic polarity detection and correction
• High-Performance host bus interface
- Simple, SRAM-like interface
- 32/16-bit data bus
- Large, 16Kbyte FIFO memory that can be
allocated to RX or TX functions
- One configurable host interrupt
• Miscellaneous features
- Low profile 100-pin, TQFP RoHS Compliant
package
- Integral 1.8V regulator
- General Purpose Timer
- Support for optional EEPROM
- Support for 3 status LEDs multiplexed with
Programmable GPIO signals
• 3.3V Power Supply with 5V tolerant I/O
• 0 to 70C
* Third-party brands and names are the property of their
respective owners.
2005-2016 Microchip Technology Inc.
DS00002266A-page 1
1 page  
LAN9118
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM UTILIZING THE MICROCHIP LAN9118
System Memory
System Memory
System
Peripherals
Microprocessor/
Microcontroller
System Bus
LAN9118
Magnetics
LEDS/GPIO
Ethernet
25MHz
XTAL
EEPROM
(Optional)
The Microchip LAN9118 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of trans-
lating parallel data from a host controller into Ethernet packets. The LAN9118 Ethernet MAC/PHY controller is designed
and optimized to function in an embedded environment. All communication is performed with programmed I/O transac-
tions using the simple SRAM-like host interface bus.
The diagram shown above, describes a typical system configuration of the LAN9118 in a typical embedded environ-
ment.
The LAN9118 is a general purpose, platform independent, Ethernet controller. The LAN9118 consists of four major func-
tional blocks. The four blocks are:
• 10/100 Ethernet PHY
• 10/100 Ethernet MAC
• RX/TX FIFOs
• Host Bus Interface (HBI)
2005-2016 Microchip Technology Inc.
DS00002266A-page 5
5 Page 
LAN9118
TABLE 2-5:
Pin No.
95
SYSTEM AND POWER SIGNALS (CONTINUED)
Name
Symbol
Buffer
Type
# Pins
Reset
nRESET
IS
(PU)
1
70 Wakeup Indicator
PME
O8/OD8
1
71,73,7
5,84,90,
91
74
Reserved
10/100 Selector
Reserved
SPEED_SEL
I (PU)
5
1
Description
Active-low reset input. Resets all logic
and registers within the LAN9118 This
signal is pulled high with a weak
internal pull-up resistor. If nRESET is
left unconnected, the LAN9118 will rely
on its internal power-on reset circuitry
Note:
The LAN9118 must always
be read at least once after
power-up, reset, or upon
return from a power-saving
state or write operations will
not function. See Section
3.11, "Detailed Reset
Description," on page 31 for
additional information
When programmed to do so, is
asserted when the LAN9118 detects a
wake event and is requesting the
system to wake up from the associated
sleep state. The polarity and buffer
type of this signal is programmable.
Note:
Detection of a Power Man-
agement Event, and asser-
tion of the PME signal will
not wakeup the LAN9118.
The LAN9118 will only wake
up when it detects a host
write cycle (assertion of
nCS and nWR). Although
any write to the LAN9118,
regardless of the data writ-
ten, will wake-up the device
when it is in a power-saving
mode, it is required that the
BYTE_TEST register be
used for this purpose.
No Connect
This signal functions as a configuration
input on power-up and is used to select
the default Ethernet settings. Upon
deassertion of reset, the value of the
input is latched. This signal functions
as shown in Table 2-2, "Default
Ethernet Settings", below.
2005-2016 Microchip Technology Inc.
DS00002266A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN9118.PDF ] | |
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