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PDF LAN89730 Data sheet ( Hoja de datos )
| Número de pieza | LAN89730 | |
| Descripción | High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet Controller | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LAN89730 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LAN89730
High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet
Controller for Automotive Applications
Highlights
• Single Chip HSIC USB 2.0 to 10/100 Ethernet
Controller
• Integrated 10/100 Ethernet MAC with Full-Duplex
Support
• Integrated 10/100 Ethernet PHY with HP Auto-
MDIX Support
• Integrated USB 2.0 Hi-Speed Device Controller
• Integrated HSIC Interface1
• Implements Reduced Power Operating Modes
Target Applications
• Diagnostic Interface
(for Dealership Service Bay)
• Fast Software Download Interface
(e.g., OBD Connector)
• Gateway Service Interface
(Dealership, Aftermarket Repair Shop)
• In-vehicle Engineering Development Interface
• Vehicle Manufacturing Test Interface
(Production Plant Assembly Line)
• Legislated Inspections
(Emissions Check, Safety Inspections)
Key Features
• USB Device Controller
- Fully compliant with Hi-Speed Universal Serial
Bus Specification, revision 2.0
- Supports HS (480 Mbps) mode
- Four Endpoints supported
- Supports vendor specific commands
- Integrated HSIC Interface
- Remote wakeup supported
• High-Performance 10/100 Ethernet Controller
- Fully compliant with IEEE 802.3/802.3u
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and half-duplex support
- Full- and half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and checking
- Automatic payload padding and pad removal
- Loop-back modes
- TCP/UDP/IP/ICMP checksum offload support
- Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Wakeup packet support
- Integrated Ethernet PHY
- Auto-negotiation
- Automatic polarity detection and correction
- HP Auto-MDIX support
- Link status change wake-up detection
- Support for three status LEDs
• Power and I/Os
- Various low power modes
- Supports PCI-like PME wake when USB host dis-
abled
- 11 GPIOs
- Supports bus-powered and self-powered opera-
tion
- Integrated power-on reset circuit
- Single external 3.3 V I/O supply
- Optional internal core regulator
• Miscellaneous Features
- EEPROM controller
- Supports custom operation without EEPROM
- IEEE 1149.1 (JTAG) boundary scan
- Requires single 25 MHz crystal
• Software
- Windows® 8/7/XP/Vista driver
- Linux® driver
- Win CE driver
- MAC® OS driver
- EEPROM utility
• Packaging
- 56-pin VQFN (8 x 8 mm), RoHS-compliant
• Environmental
- -40°C to +85°C temperature range
1. Compliant to HSIC ECN as of May 2010
2013-2015 Microchip Technology Inc.
DS60001348A-page 1
1 page  
LAN89730
1.0 INTRODUCTION
1.1 General Terms
Byte
CSR
DWORD
FCT
FIFO
Frame
FSM
GPIO
HSIC
Host
Level-Triggered Sticky Bit
LFSR
MAC
MII
N/A
Packet
POR
RESERVED
SCSR
SMI
TLI
URX
UTX
WORD
ZLP
8 bits
Control and Status Registers
32 bits
FIFO Controller
First In First Out buffer
In the context of this document, a frame refers to transfers on the Ethernet
interface.
Finite State Machine
General Purpose I/O
High-Speed Inter-Chip
External system (includes processor, application software, etc.)
This type of status bit is set whenever the condition that it represents is
asserted. The bit remains set until the condition is no longer true and the sta-
tus bit is cleared by writing a zero.
Linear Feedback Shift Register
Media Access Controller
Media Independent Interface
Not Applicable
In the context of this document, a packet refers to transfers on the USB inter-
face.
Power on Reset
Refers to a reserved bit field or address. Unless otherwise noted, reserved
bits must always be zero for write operations. Unless otherwise noted, values
are not ensured when reading reserved bits. Unless otherwise noted, do not
read or write to reserved addresses.
System Control and Status Register
Serial Management Interface
Transaction Layer Interface
USB Bulk-Out Packet Receiver
USB Bulk-In Packet Transmitter
16 bits
Zero Length USB Packet
2013-2015 Microchip Technology Inc.
DS60001348A-page 5
5 Page 
2.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
PIN ASSIGNMENTS (TOP VIEW)
LAN89730
nPHY_INT 1
TXN 2
TXP 3
VDD33A 4
RXN 5
RXP 6
EXRES 7
VDD33A 8
VDD12PLL 9
HSIC_DATA 10
HSIC_STROBE 11
VDD12A 12
TEST2 13
NC 14
LAN89730AM
lllryyww
ttttttttt
cc
42 RXDV
41 RXCLK
40 TDI/RXD3
39 TMS/RXD2
38 TCK/RXD1
37 TDO/nPHY_RST
36 nTRST/RXD0
35 VDD33IO
34 PHY_SEL
33 TEST1
32 EEDI
31 EEDO/AUTOMDIX_EN
30 EECS
29 EECLK
The package designators are:
• lll - Lot sequence code (optional)
• r - Chip revision number
• yy - Last two digits of assembly year
• ww - Assembly work week
• tttttttttttt - Tracking number (up to 9 characters)
• cc - Country of original abbreviation (optional - up to 2 characters)
Note:
Note:
Note:
Note:
** This pin provides additional PME related functionality. Refer to the respective pin descriptions and Chapter
5.0, "PME Operation" for additional information.
*** GPIO7 may provide additional PHY Link Up related functionality. Refer to Section 4.12.2.4, "Enabling
External PHY Link Up Wake Events" for additional information.
When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa.
Exposed pad (VSS) on bottom of package must be connected to ground.
2013-2015 Microchip Technology Inc.
DS60001348A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN89730.PDF ] | |
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