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PDF LAN89218 Data sheet ( Hoja de datos )

Número de pieza LAN89218
Descripción High-Performance Single-Chip 10/100 Ethernet Controller
Fabricantes Microchip 
Logotipo Microchip Logotipo



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No Preview Available ! LAN89218 Hoja de datos, Descripción, Manual

LAN89218
High-Performance Single-Chip 10/100 Ethernet Controller
for Automotive Applications
Highlights
• Designed and tested for automotive grade appli-
cations
• Integrated 10/100 MAC, PHY with HP Auto-MDIX
support
• Interfaces to most 32-bit and 16-bit embedded
CPU’s
• Integrated checksum offload engine
• Efficient architecture with low CPU overhead
• AEC-Q100 compliant
- Parts are tested to meet or exceed the
requirements of the AEC-Q100 automotive
qualification standards
Applications
• Diagnostic interface
(for dealership service bay)
• Fast software download interface
(e.g. OBD connector)
• Gateway service interface
(dealership, aftermarket repair shop)
• In-vehicle engineering development interface
• Vehicle manufacturing test interface
(production plant assembly line)
• Legislated inspections
(emissions check, safety inspections)
Features
• Non-PCI Ethernet controller for high performance
applications
- 32-bit interface with fast bus cycle times
- Burst-mode read support
• Single chip Ethernet controller
- Fully compliant with IEEE 802.3/802.3u stan-
dards
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
• High-performance host bus interface
- Simple, SRAM-like interface interfaces to
most embedded CPUs or SoCs
- 32 or 16-bit data bus
- 16 kbyte FIFO with flexible TX/RX allocation
- One configurable host interrupt
• Minimizes CPU overhead
- Supports Slave-DMA
• Supports reduced power modes
- Numerous power management modes
- Wake on LAN
- Magic packet wakeup
- Wakeup indicator event signal
- Link status change
• Eliminates dropped packets
- Internal buffer memory can store over 200
packets
- Automatic PAUSE and back-pressure flow
control
• Flexible address filtering modes
- One 48-bit perfect address
- 64 hash filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets
• Integrated 1.8 V regulator
• Optional EEPROM interface
• Mixed endian support
• General purpose timer
• Support for 3 status LEDs multiplexed with pro-
grammable GPIO signals
• Single 3.3 V Power Supply with 5.0 V tolerant I/O
• Low profile 100-pin LQFP, RoHS-compliant pack-
age
• -40C to +85C Automotive Grade Temp. Support
2008-2015 Microchip Technology Inc.
DS60001255B-page 1

1 page




LAN89218 pdf
LAN89218
1.0 GENERAL DESCRIPTION
The LAN89218 is a full-featured, single-chip 10/100 Ethernet controller that has been designed to provide the highest
performance possible for 32/16-bit applications. The LAN89218 includes an integrated Ethernet MAC and PHY with
a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-
less connection to most common 16-bit and 32-bit microprocessors and microcontrollers. The integrated checksum
offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames,
offloading the task from the CPU. The LAN89218 also includes large transmit and receive data FIFOs with a high-
speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN89218
memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity.
Applications
The LAN89218 is well suited for many high performance automotive applications, including:
• Diagnostic interface (for dealership service bay)
• Fast software download interface (e.g. OBD connector)
• Gateway service interface (dealership, aftermarket repair shop)
• In-vehicle engineering development interface
• Vehicle manufacturing test interface (production plant assembly line)
• Legislated inspections (emissions check, safety inspections)
The LAN89218 also supports features which reduce or eliminate packet loss. Its internal 16-kByte SRAM can hold
over 200 received packets. If the receive FIFO gets too full, the LAN89218 can automatically generate flow control
packets to the remote node, or assert back-pressure on the remote node by generating network collisions.
The LAN89218 supports numerous power management and wakeup features. The LAN89218 can be placed in a
reduced power mode and can be programmed to issue an external wake signal via several methods, including “Magic
Packet”, “Wake on LAN” and “Link Status Change”. This signal is ideal for triggering system power-up using remote
Ethernet wakeup events. The device can be removed from the low power state via a host processor command.
The LAN89218 integrated 10/100 MAC/PHY controller performs the function of translating parallel data from a host
controller into Ethernet packets. The LAN89218 Ethernet MAC/PHY controller is designed and optimized to function
in an embedded environment. All communication is performed with programmed I/O transactions using the simple
SRAM-like host interface bus.
2008-2015 Microchip Technology Inc.
DS60001255B-page 5

5 Page





LAN89218 arduino
LAN89218
TABLE 2-3: SERIAL EEPROM INTERFACE SIGNALS
Name
EEPROM Data,
GPO3, TX_EN,
TX_CLK,
D32/nD16
Symbol
EEDIO/GPO3/
TX_EN/TX_CLK
(D32/nD16)
Buffer Type
I/O8
EEPROM Chip
Select
EEPROM Clock,
GPO4 RX_DV,
RX_CLK
EECS
EECLK/GPO4/
RX_DV/RX_CLK
O8
O8
# Pins
1
1
Description
EEPROM Data: This bi-directional pin can be
connected to a serial EEPROM DIO. This is
optional.
General Purpose Output 3: This pin can also
function as a general purpose output, or it can be
configured to monitor the TX_EN or TX_CLK sig-
nals on the internal MII port. When configured as
a GPO signal, or as a TX_EN/TX_CLK monitor,
the EECS pin is deasserted so as to never unin-
tentionally access the serial EEPROM. This sig-
nal cannot function as a general-purpose input.
Data Bus Width Select: This signal also func-
tions as a configuration input on power-up and is
used to select the host bus data width. Upon
deassertion of reset, the value of the input is
latched. When high, a 32-bit data bus is utilized.
When low, a 16-bit interface is utilized.
Serial EEPROM chip select.
1 EEPROM Clock: Serial EEPROM Clock pin.
General Purpose Output 4: This pin can also
function as a general-purpose output, or it can be
configured to monitor the RX_DV or RX_CLK
signals on the internal MII port. When configured
as a GPO signal, or as an RX_DV/RX_CLK mon-
itor, the EECS pin is deasserted so as to never
unintentionally access the serial EEPROM. This
signal cannot function as a general-purpose
input.
Note:
When the EEPROM interface is not
used, the EECLK pin must be left
unconnected.
Note:
This pin must not be pulled low by an
external resistor or driven low exter-
nally under any conditions.
2008-2015 Microchip Technology Inc.
DS60001255B-page 11

11 Page







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