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PDF LAN8741A Data sheet ( Hoja de datos )
| Número de pieza | LAN8741A | |
| Descripción | Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LAN8741A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LAN8741A/LAN8741Ai
Small Footprint MII/RMII 10/100 Energy Efficient Ethernet
Transceiver with HP Auto-MDIX and flexPWR® Technology
Highlights
• Single-Chip Ethernet Physical Layer Transceiver
(PHY)
• Compliant with Energy Efficient Ethernet 802.3az
• Comprehensive flexPWR technology
- Flexible power management architecture
- LVCMOS Variable I/O voltage range: +1.8 V to
+3.3 V
- Integrated 1.2 V regulator with disable feature
• HP Auto-MDIX support
• Small footprint 32-pin VQFN, RoHS-compliant
package (5 x 5 x 0.9 mm height)
• Deterministic 100 Mb internal loopback latency
(MII Mode)
Target Applications
• Set-Top Boxes
• Networked Printers and Servers
• Test Instrumentation
• LAN on Motherboard
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adapters/Servers
• Gaming Consoles
• POE Applications
(Refer to Microchip Application Note 17.18)
Key Benefits
• High-performance 10/100 Ethernet transceiver
- Compliant with IEEE802.3/802.3u (Fast Ethernet)
- Compliant with ISO 802-3/IEEE 802.3
(10BASE-T)
- Compliant with Energy Efficient Ethernet IEEE
802.3az
- Loop-back modes
- Auto-negotiation
- Automatic polarity detection and correction
- Link status change wake-up detection
- Vendor specific register functions
- Supports both MII and the reduced pin count RMII
interface
• Power and I/Os
- Various low power modes
- Integrated power-on reset circuit
- Two status LED outputs
- May be used with a single 3.3 V supply
• Additional Features
- Ability to use a low cost 25 MHz crystal for
reduced BOM
• Packaging
- 32-pin VQFN (5 x 5 mm), RoHS-compliant
package with MII and RMII
• Environmental
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C)
2013-2015 Microchip Technology Inc.
DS00001988A-page 1
1 page  
LAN8741A/LAN8741Ai
FIGURE 1-2:
ARCHITECTURAL OVERVIEW
MODE[0:2]
nRST
RMIISEL
TXD[0:3]
TXEN
TXER
TXCLK
RXD[0:3]
RXDV
RXER
RXCLK
CRS
COL/CRS_DV
MDC
MDIO
Mode Control
Reset Control
Auto-
Negotiation
SMI Management
Control
100M RX
Logic
10M RX
Logic
100M TX
Logic
100M
Transmitter
Transmitter
10M TX
Logic
10M
Transmitter
DSP System:
Clock
Data Recovery
Equalizer
Receiver
10M PLL
Analog-to-
Digital
100M PLL
Squeltch
& Filters
LAN8741A/LAN8741Ai
HP Auto-MDIX
TXP/TXN
RXP/RXN
MDIX
Control
PLL
Interrupt
Generator
LEDs
XTAL1/CLKIN
XTAL2
nINT
LED1
LED2
Central Bias
RBIAS
PHY Address
Latches
PHYAD[0:2]
2013-2015 Microchip Technology Inc.
DS00001988A-page 5
5 Page 
LAN8741A/LAN8741Ai
Note 1: Configuration strap values are latched on power-on reset and system reset. Configuration straps are iden-
tified by an underlined symbol name. Signals that function as configuration straps must be augmented with
an external resistor when connected to a load. Refer to Section 3.7, "Configuration Straps" for additional
information.
TABLE 2-3: SERIAL MANAGEMENT INTERFACE (SMI) PINS
Num Pins
1
Name
SMI Data
Input/Output
1 SMI Clock
Symbol
MDIO
MDC
Buffer Type
Description
VIS/
VO8
(PU)
VIS
Serial Management Interface data input/output
Serial Management Interface clock
TABLE 2-4: ETHERNET PINS
Num Pins
1
1
1
1
Name
Ethernet
TX/RX Posi-
tive Channel
1
Ethernet
TX/RX Nega-
tive Channel
1
Ethernet
TX/RX Posi-
tive Channel
2
Ethernet
TX/RX Nega-
tive Channel
2
Symbol
TXP
TXN
RXP
RXN
Buffer Type
Description
AIO Transmit/Receive Positive Channel 1
AIO Transmit/Receive Negative Channel 1
AIO Transmit/Receive Positive Channel 2
AIO Transmit/Receive Negative Channel 2
TABLE 2-5:
Num Pins
1
1
1
MISCELLANEOUS PINS
Name
External
Crystal
Input
External
Clock Input
Symbol
XTAL1
CLKIN
External
Crystal Out-
put
External
Reset
XTAL2
nRST
Buffer Type
Description
ICLK
External crystal input
ICLK
OCLK
Single-ended clock oscillator input.
Note:
When using a single ended clock
oscillator, XTAL2 should be left uncon-
nected.
External crystal output
VIS
(PU)
System reset. This signal is active low.
2013-2015 Microchip Technology Inc.
DS00001988A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN8741A.PDF ] | |
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