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PDF LAN8700i Data sheet ( Hoja de datos )
| Número de pieza | LAN8700i | |
| Descripción | MII/RMII 10/100 Ethernet Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LAN8700i (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LAN8700/LAN8700i
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with
HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Highlights
• Single-Chip Ethernet Physical Layer Transceiver
(PHY)
• ESD Protection levels of ±8kV HBM without exter-
nal protection devices
• ESD protection levels of EN/IEC61000-4-2, ±8kV
contact mode, and ±15kV for air discharge mode
per independent test facility
• Comprehensive flexPWR® Technology
- Flexible Power Management Architecture
• LVCMOS Variable I/O voltage range: +1.6V to
+3.6V
• Integrated 3.3V to 1.8V regulator for optional sin-
gle supply operation.
- Regulator can be disabled if 1.8V system
supply is available.
• Performs HP Auto-MDIX in accordance with IEEE
802.3ab specification
• Cable length greater than 150 meters
• Automatic Polarity Correction
• Latch-Up Performance Exceeds 150mA per EIA/
JESD 78, Class II
• Energy Detect power-down mode
• Low Current consumption power down mode
• Low operating current consumption:
- 39mA typical in 10BASE-T and
- 79mA typical in 100BASE-TX mode
• Supports Auto-negotiation and Parallel Detection
• Supports the Media Independent Interface (MII)
and Reduced Media Independent Interface (RMII)
• Compliant with IEEE 802.3-2005 standards
- MII Pins tolerant to 3.6V
• IEEE 802.3-2005 compliant register functions
• Integrated DSP with Adaptive Equalizer
• Baseline Wander (BLW) Correction
• Vendor Specific register functions
• Low profile 36-pin QFN RoHS compliant package
(6 x 6 x 0.9mm height)
• 4 LED status indicators
• Commercial Operating Temperature 0 C to 70 C
• Industrial Operating Temperature -40 C to 85 C
version available (LAN8700i)
Applications
• Set Top Boxes
• Network Printers and Servers
• LAN on Motherboard
• 10/100 PCMCIA/CardBus Applications
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• Personal Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adaptors/Servers
• POS Terminals
• Automotive Networking
• Gaming Consoles
• Security Systems
• POE Applications
• Access Control
2007-2016 Microchip Technology Inc.
DS00002260A-page 1
1 page  
LAN8700/LAN8700i
FIGURE 1-2:
LAN8700/LAN8700I ARCHITECTURAL OVERVIEW
MODE0
MODE1
MODE2
nRST
MII
MODE Control
SMI
Auto-
Negotiation
Management
Control
10M Tx
Logic
10M
Transmitter
Transmit Section
100M Tx
Logic
100M
Transmitter
TXD[0..3]
TX_EN
TX_ER
TX_CLK
RXD[0..3]
RX_DV
RX_ER
RX_CLK
CRS
COL/CRS_DV
MDC
MDIO
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Receive Section
Analog-to-
Digital
100M PLL
10M Rx
Logic
Squelch &
Filters
10M PLL
HP Auto-MDIX
TXP / TXN
RXP / RXN
MDIX
Control
PLL
PHY
Address
Latches
Interrupt
Generator
LED Circuitry
Central
Bias
XTAL1
XTAL2
nINT
PHYAD[0..4]
SPEED100
LINK
ACTIVITY
FDUPLEX
2007-2016 Microchip Technology Inc.
DS00002260A-page 5
5 Page 
LAN8700/LAN8700i
TABLE 3-4: BOOT STRAP CONFIGURATION INPUTS (Note 3-1)
Signal Name
Type
Description
CRS/
PHYAD4
FDUPLEX/
PHYAD3
ACTIVITY/
PHYAD2
LINK/
PHYAD1
SPEED100/
PHYAD0
RXD2/
MODE2
RXD1/
MODE1
RXD0/
MODE0
COL/
RMII/
CRS_DV
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IOPD
PHY Address Bit 4: set the default address of the PHY. This
signal is mux’d with CRS
Note: This signal is mux’d with CRS
PHY Address Bit 3: set the default address of the PHY.
Note: This signal is mux’d with FDUPLEX
PHY Address Bit 2: set the default address of the PHY.
Note: This signal is mux’d with ACTIVITY
PHY Address Bit 1: set the default address of the PHY.
Note: This signal is mux’d with LINK
PHY Address Bit 0: set the default address of the PHY.
Note: This signal is mux’d with SPEED100
PHY Operating Mode Bit 2: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 46, for the
MODE options.
Note: This signal is mux’d with RXD2
PHY Operating Mode Bit 1: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 46, for the
MODE options.
Note: This signal is mux’d with RXD1
PHY Operating Mode Bit 0: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 46, for the
MODE options.
Note: This signal is mux’d with RXD0
Digital Communication Mode: set the digital communications
mode of the PHY to RMII or MII. This signal is muxed with the
Collision signal (MII mode) and Carrier Sense/ receive Data Valid
(RMII mode)
• Float for MII mode.
• Pull up with a resistor to VDDIO for RMII mode (see Table 4-3,
“Boot Strapping Configuration Resistors,” on page 25)
RXD3/
nINTSEL
IOPU
nINT pin mode select: set the mode of pin 1.
• Default, left floating pin 1 is nINT, active low interrupt output.
• For nINT mode, tie nINT/TXD4/TXER to VDDIO with a resistor
(see Table 4-3, “Boot Strapping Configuration Resistors,” on
page 25).
• Pulled to VSS by a resistor, (see Table 4-3, “Boot Strapping
Configuration Resistors,” on page 25) pin 1 is TX_ER/TXD4,
Transmit Error or Transmit data 4 (5B mode).
• For TXD4/TXER mode, do not tie nINT/TXD4/TXER to VDDIO
or Ground.
Note 3-1 On nRST transition high, the PHY latches the state of the configuration pins in this table.
2007-2016 Microchip Technology Inc.
DS00002260A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN8700i.PDF ] | |
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