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PDF KSZ8081RND Data sheet ( Hoja de datos )

Número de pieza KSZ8081RND
Descripción 10BASE-T/100BASE-TX PHY
Fabricantes Microchip 
Logotipo Microchip Logotipo



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No Preview Available ! KSZ8081RND Hoja de datos, Descripción, Manual

KSZ8081RNA/RND
10BASE-T/100BASE-TX PHY with RMII
Support
Features
• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
• RMII v1.2 Interface Support with a 50 MHz Refer-
ence Clock Output to MAC, and an Option to
Input a 50 MHz Reference Clock
• RMII Back-to-Back Mode Support for a 100 Mbps
Copper Repeater
• MDC/MDIO Management Interface for PHY Reg-
ister Configuration
• Programmable Interrupt Output
• LED Outputs for Link and Activity Status Indica-
tion
• On-Chip Termination Resistors for the Differential
Pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X to Reliably Detect and Cor-
rect Straight-Through and Crossover Cable Con-
nections with Disable and Enable Option
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100 Mbps) and
Duplex (Half/Full)
• Power-Down and Power-Saving Modes
• LinkMD® TDR-Based Cable Diagnostics to Iden-
tify Faulty Copper Cabling
• Parametric NAND Tree Support for Fault Detec-
tion Between Chip I/Os and the Board
• HBM ESD Rating (6 kV)
• Loopback Modes for Diagnostics
• Single 3.3V Power Supply with VDD I/O Options
for 1.8V, 2.5V, or 3.3V
• Built-In 1.2V Regulator for Core
• Available in 24-pin 4 mm x 4 mm QFN Package
Target Applications
• Game Consoles
• IP Phones
• IP Set-Top Boxes
• IP TVs
• LOM
• Printers
2016 Microchip Technology Inc.
DS00002199A-page 1

1 page




KSZ8081RND pdf
KSZ8081RNA/RND
2.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
24-QFN PIN ASSIGNMENT (TOP VIEW)
24 23 22 21 20 19
VDD_1.2 1
VDDA_3.3 2
RXM 3
RXP 4
TXM 5
TXP 6
PADDLE GROUND
(ON BOTTOM OF CHIP)
18 INTRP
17 RXER
16 REF_CLK
15 CRS_DV/
PHYAD[1:0]
14 VDDIO
13 RXD0
7 8 9 10 11 12
2016 Microchip Technology Inc.
DS00002199A-page 5

5 Page





KSZ8081RND arduino
KSZ8081RNA/RND
3.1.5 10BASE-T RECEIVE
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent
noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8081RNA/RND decodes a data frame. The receive clock is kept active
during idle periods between data receptions.
3.1.6 PLL CLOCK SYNTHESIZER
The KSZ8081RNA/RND in RMII – 25 MHz Clock mode generates all internal clocks and all external clocks for system
timing from an external 25 MHz crystal, oscillator, or reference clock. For the KSZ8081RNA/RND in RMII – 50 MHz
clock mode, these clocks are generated from an external 50 MHz oscillator or system clock.
3.1.7 AUTO-NEGOTIATION
The KSZ8081RNA/RND conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specifica-
tion.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
• Priority 1: 100BASE-TX, full-duplex
• Priority 2: 100BASE-TX, half-duplex
• Priority 3: 10BASE-T, full-duplex
• Priority 4: 10BASE-T, half-duplex
If auto-negotiation is not supported or the KSZ8081RNA/RND link partner is forced to bypass auto-negotiation, then the
KSZ8081RNA/RND sets its operating mode by observing the signal at its receiver. This is known as parallel detection,
which allows the KSZ8081RNA/RND to establish a link by listening for a fixed signal protocol in the absence of the auto-
negotiation advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (ANEN_SPEED, Pin 23) or software (Register 0h, Bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by Register 0h, Bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, Bit [13], and the duplex
is set by Register 0h, Bit [8].
The auto-negotiation link-up process is shown in Figure 3-1.
2016 Microchip Technology Inc.
DS00002199A-page 11

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